SN74HSTL16918 9 位至 18 位 HSTL-To-LVTTL 存储器地址锁存器

This 9-bit to 18-bit D-type latch is designed for 3.15-V to 3.45-V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels.

The SN74HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE\) input.

Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE\ is low, the Q outputs of the corresponding nine latches follow the D inputs. When LE\ is taken high, the Q outputs are latched at the levels set up at the D inputs.

The SN74HSTL16918 is characterized for operation from 0°C to 70°C

	SN74HSTL16918
Voltage Nodes(V)	3.3
Input Level	HSTL
Output Level	LVTTL
Technology Family	HSTL
Rating	Catalog

SN74HSTL16918 特性

• Member of the Texas Instruments WidebusTM Family
• Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• Packaged in Plastic Thin Shrink Small-Outline Package

SN74HSTL16918 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
74HSTL16918DGGRG4	ACTIVE	-40 to 85	4.40 | 1ku	TSSOP (DGG) | 48	2000 | LARGE T&R
SN74HSTL16918DGGR	ACTIVE	-40 to 85	4.40 | 1ku	TSSOP (DGG) | 48	2000 | LARGE T&R

SN74HSTL16918 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
74HSTL16918DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74HSTL16918DGGRG4	74HSTL16918DGGRG4
SN74HSTL16918DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74HSTL16918DGGR	SN74HSTL16918DGGR

SN74HSTL16918 应用技术支持与电子电路设计开发资源下载

1. SN74HSTL16918 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)