SN74HC74-EP 具有清零和预设功能的增强型产品双路 D 类上升沿触发器

The SN74HC74 device contains two independent D-type positive edge triggered flip flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold time interval, data at the D input can be changed without affecting the levels at the outputs.

	SN74HC74-EP
tpd max(ns)	345
tsu(ns)	150
Technology Family	HC
Rating	HiRel Enhanced Product

SN74HC74-EP 特性

• Controlled Baseline
  • One Assembly Site
  • One Test Site
  • One Fabrication Site
• Extended Temperature Performance of -55°C to 125°C
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree(1)
• Wide Operating Voltage Range of 2 V to 6 V
• Outputs Can Drive Up To 10 LSTTL Loads
• Low Power Consumption, 80 uA Max ICC
• Typical tpd = 15 ns
• ±4 mA Output Drive at 5 V
• Low Input Current of 1 mA Max

SN74HC74-EP 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74HC74MPWREP	ACTIVE	-55 to 125	0.46 | 1ku	TSSOP (PW) | 14	2000 | LARGE T&R
V62/08613-01XE	ACTIVE	-55 to 125	0.46 | 1ku	TSSOP (PW) | 14	2000 | LARGE T&R

SN74HC74-EP 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74HC74MPWREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74HC74MPWREP	SN74HC74MPWREP
V62/08613-01XE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/08613-01XE	V62/08613-01XE

SN74HC74-EP 应用技术支持与电子电路设计开发资源下载

1. SN74HC74-EP 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)