SN74HC574 具有三态输出的八路 D 类边沿触发器
These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect the internal operations of the flip-flops
| SN74HC574 | |
| Voltage Nodes(V) | 6, 5, 2 |
| Vcc range(V) | 2.0 to 6.0 |
| Input Level | CMOS |
| Output Level | CMOS |
| Output Drive(mA) | -6/6 |
| No. of Outputs | 8 |
| th(ns) | 5 |
| tpd max(ns) | 38 |
| tsu(ns) | 21 |
| Logic | True |
| Technology Family | HC |
| Rating | Catalog |
SN74HC574 特性
- Wide Operating Voltage Range of 2 V to 6 V
- High-Current 3-State Noninverting Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads
- Low Power Consumption, 80-uA Max ICC
- Typical tpd = 22 ns
- ±6-mA Output Drive at 5 V
- Low Input Current of 1 uA Max
- Bus-Structured Pinout
SN74HC574 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74HC574DW | ACTIVE | 0 to 70 | 1.10 | 1ku | SOIC (DW) | 20 | 25 | TUBE | HC574 |
| SN74HC574DWE4 | ACTIVE | 0 to 70 | 1.10 | 1ku | SOIC (DW) | 20 | 25 | TUBE | HC574 |
| SN74HC574DWG4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (DW) | 20 | 2000 | LARGE T&R | HC574 |
| SN74HC574DWR | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (DW) | 20 | 2000 | LARGE T&R | HC574 |
| SN74HC574DWRE4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (DW) | 20 | 2000 | LARGE T&R | HC574 |
| SN74HC574DWRG4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (DW) | 20 | 2000 | LARGE T&R | HC574 |
| SN74HC574N | ACTIVE | 0 to 70 | 1.00 | 1ku | PDIP (N) | 20 | 20 | TUBE | SN74HC574N |
| SN74HC574N3 | OBSOLETE | 0 to 70 | PDIP (N) | 20 | SN74HC574N | ||
| SN74HC574NE4 | ACTIVE | 0 to 70 | 1.00 | 1ku | PDIP (N) | 20 | 20 | TUBE | SN74HC574N |
| SN74HC574NSR | ACTIVE | 0 to 70 | 1.00 | 1ku | SO (NS) | 20 | 2000 | LARGE T&R | HC574 |
| SN74HC574NSRE4 | ACTIVE | 0 to 70 | 1.00 | 1ku | SO (NS) | 20 | 2000 | LARGE T&R | HC574 |
| SN74HC574NSRG4 | ACTIVE | 0 to 70 | 1.00 | 1ku | SO (NS) | 20 | 2000 | LARGE T&R | HC574 |
SN74HC574 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74HC574DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574DW | SN74HC574DW |
| SN74HC574DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574DWE4 | SN74HC574DWE4 |
| SN74HC574DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574DWG4 | SN74HC574DWG4 |
| SN74HC574DWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574DWR | SN74HC574DWR |
| SN74HC574DWRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574DWRE4 | SN74HC574DWRE4 |
| SN74HC574DWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574DWRG4 | SN74HC574DWRG4 |
| SN74HC574N | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574N | SN74HC574N |
| SN74HC574N3 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74HC574N3 | SN74HC574N3 |
| SN74HC574NE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74HC574NE4 | SN74HC574NE4 |
| SN74HC574NSR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574NSR | SN74HC574NSR |
| SN74HC574NSRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574NSRE4 | SN74HC574NSRE4 |
| SN74HC574NSRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC574NSRG4 | SN74HC574NSRG4 |
SN74HC574 应用技术支持与电子电路设计开发资源下载
- SN74HC574 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)