This circuit is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output
SN74HC273-Q1 | |
Voltage Nodes(V) | 5 |
Rating | Catalog |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN74HC273QDWRG4Q1 | ACTIVE | -40 to 125 | 0.27 | 1ku | SOIC (DW) | 20 | 2000 | |
SN74HC273QDWRQ1 | ACTIVE | -40 to 125 | 0.27 | 1ku | SOIC (DW) | 20 | 2000 | |
SN74HC273QPWRG4Q1 | ACTIVE | -40 to 125 | 0.27 | 1ku | TSSOP (PW) | 20 | 2000 | |
SN74HC273QPWRQ1 | ACTIVE | -40 to 125 | 0.27 | 1ku | TSSOP (PW) | 20 | 2000 |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN74HC273QDWRG4Q1 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC273QDWRG4Q1 | SN74HC273QDWRG4Q1 |
SN74HC273QDWRQ1 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC273QDWRQ1 | SN74HC273QDWRQ1 |
SN74HC273QPWRG4Q1 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC273QPWRG4Q1 | SN74HC273QPWRG4Q1 |
SN74HC273QPWRQ1 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC273QPWRQ1 | SN74HC273QPWRQ1 |