Each data selector/multiplexer contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output-control inputs are provided for each of the two 4-line sections.
The 3-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (in the high-impedance state), the low impedance of the single enabled output drives the bus line to a high or low logic level. Each output has its own output-enable (OE) input. The outputs are disabled when their respective OE is high
SN74HC253-Q1 | |
Rating | Automotive |
Technology Family | HC |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN74HC253QDRG4Q1 | ACTIVE | -40 to 125 | 0.30 | 1ku | SOIC (D) | 16 | 2500 | |
SN74HC253QDRQ1 | ACTIVE | -40 to 125 | 0.30 | 1ku | SOIC (D) | 16 | 2500 |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN74HC253QDRG4Q1 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC253QDRG4Q1 | SN74HC253QDRG4Q1 |
SN74HC253QDRQ1 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HC253QDRQ1 | SN74HC253QDRQ1 |