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SN74HC165-EP 增强型产品 8 位并行负载移位寄存器

The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shifts the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HC165 device also features a clock-inhibit (CLK INH) function and a complementary serial (QH) output.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD\ is held high

SN74HC165-EP
Technology Family HC
Rating HiRel Enhanced Product
SN74HC165-EP 特性
SN74HC165-EP 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74HC165QDREP ACTIVE -40 to 125 0.41 | 1ku SOIC (D) | 16 2500 | LARGE T&R  
SN74HC165QPWREP ACTIVE -40 to 125 0.41 | 1ku TSSOP (PW) | 16 2000 | LARGE T&R  
V62/04689-01XE ACTIVE -40 to 125 0.41 | 1ku SOIC (D) | 16 2500 | LARGE T&R  
V62/04689-01YE ACTIVE -40 to 125 0.41 | 1ku TSSOP (PW) | 16 2000 | LARGE T&R  
SN74HC165-EP 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74HC165QDREP Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC165QDREP SN74HC165QDREP
SN74HC165QPWREP Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC165QPWREP SN74HC165QPWREP
V62/04689-01XE Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04689-01XE V62/04689-01XE
V62/04689-01YE Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04689-01YE V62/04689-01YE
SN74HC165-EP 应用技术支持与电子电路设计开发资源下载
  1. SN74HC165-EP 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)