SN74GTLPH1612 18 位 LVTTL 到 GTLP 可调节边缘速率通用总线收发器
The SN74GTLPH1612 is a high-drive, 18-bit UBTTM transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OECTM circuitry, and TI-OPCTM circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models.
|
SN74GTLPH1612 |
| Voltage Nodes(V) |
3.3 |
| A Side |
LVTTL |
| B Side |
GTL |
| No. of Bits |
18 |
| Static Current |
45 |
| Rating |
Catalog |
| Technology Family |
GTLP |
SN74GTLPH1612 特性
- Member of the Texas Instruments' WidebusTM Family
- UBTTM Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
- TI-OPCTM Circuitry Limits Ringing on Unevenly Loaded Backplanes
- OECTM Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
- Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
- LVTTL Interfaces Are 5-V Tolerant
- High-Drive GTLP Outputs (100 mA)
- LVTTL Outputs (\x9624 mA/24 mA)
- Variable Edge-Rate Control (ERC\) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
- Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
- Bus Hold on A-Port Data Inputs
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74GTLPH1612 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 74GTLPH1612DGGRE4 |
ACTIVE |
-40 to 85 |
7.65 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
| 74GTLPH1612DGGRG4 |
ACTIVE |
-40 to 85 |
7.65 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
| SN74GTLPH1612DGGR |
ACTIVE |
-40 to 85 |
7.65 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
SN74GTLPH1612 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 74GTLPH1612DGGRE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74GTLPH1612DGGRE4 |
74GTLPH1612DGGRE4 |
| 74GTLPH1612DGGRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74GTLPH1612DGGRG4 |
74GTLPH1612DGGRG4 |
| SN74GTLPH1612DGGR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTLPH1612DGGR |
SN74GTLPH1612DGGR |
SN74GTLPH1612 应用技术支持与电子电路设计开发资源下载
- SN74GTLPH1612 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)