SN74GTL2003 8 位双向低电压转换器
The SN74GTL2003 provides eight NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).
When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pullup resistors
|
SN74GTL2003 |
| No. of Bits |
8 |
| No. of Outputs |
8 |
| Bus Drive(Max)(ma) |
64 |
| Static Current(Max)(mA) |
0.005 |
| tpd max(ns) |
1.5 |
| Voltage Nodes(Nom)(V) |
1 to 5 |
| Operating Temperature Range(°C) |
-40 to 85 |
| Pin/Package |
20TSSOP, 20VQFN |
| Technology Family |
TVC |
SN74GTL2003 特性
- Provides Bidirectional Voltage Translation
With No Direction Control Required
- Allows Voltage Level Translation From 1 V up to 5 V
- Provides Direct Interface With GTL, GTL+,
LVTTL/TTL, and 5-V CMOS Levels
- Low On-State Resistance Between Input and
Output Pins (Sn/Dn)
- Supports Hot Insertion
- No Power Supply Required – Will Not Latch Up
- 5-V-Tolerant Inputs
- Low Standby Current
- Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II)
- 1000-V Charged-Device Model (C101)
- APPLICATIONS
- Bidirectional or Unidirectional Applications Requiring
Voltage-Level Translation From Any Voltage (1 V to 5 V) to
Any Voltage (1 V to 5 V)
- Low Voltage Processor I2C Port Translation
to 3.3-V and/or 5-V I2C Bus Signal Levels
- GTL/GTL+ Translation to LVTTL/TTL Signal Levels
SN74GTL2003 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74GTL2003PW |
ACTIVE |
-40 to 85 |
1.75 | 1ku |
TSSOP (PW) | 20 |
70 | BULK |
|
| SN74GTL2003PWR |
ACTIVE |
-40 to 85 |
1.45 | 1ku |
TSSOP (PW) | 20 |
2000 | LARGE T&R |
|
| SN74GTL2003RKSR |
ACTIVE |
-40 to 85 |
1.75 | 1ku |
VQFN (RKS) | 20 |
3000 | LARGE T&R |
|
SN74GTL2003 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74GTL2003PW |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTL2003PW |
SN74GTL2003PW |
| SN74GTL2003PWR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTL2003PWR |
SN74GTL2003PWR |
| SN74GTL2003RKSR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTL2003RKSR |
SN74GTL2003RKSR |
SN74GTL2003 应用技术支持与电子电路设计开发资源下载
- SN74GTL2003 数据资料 dataSheet 下载.PDF
- TI 德州仪器电压电平转换产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)