SN74F1056 8 位肖特基势垒二极管总线终端阵列
This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines. This device consists of an 8-bit high-speed Schottky diode array suitable for a clamp to GND.
The SN74F1056 is characterized for operation from 0°C to 70°C
| SN74F1056 | |
| Voltage Nodes(V) | 5 |
| No. of Bits | 8 |
| Vf(Max)(V) | 1.0 |
| Vf (max)(V) | 1.0 |
| trr(max)(ns) | 7 |
| Technology Family | F |
SN74F1056 特性
- Designed to Reduce Reflection Noise
- Repetitive Peak Forward Current...300mA
- 8-Bit Array Structure Suited for Bus-Oriented Systems
SN74F1056 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74F1056D | ACTIVE | 0 to 70 | 5.10 | 1ku | SOIC (DW) | 16 | 25 | TUBE | |
| SN74F1056DE4 | ACTIVE | 0 to 70 | 5.10 | 1ku | SOIC (DW) | 16 | 25 | TUBE | |
| SN74F1056DG4 | ACTIVE | 0 to 70 | 5.10 | 1ku | SOIC (DW) | 16 | 25 | TUBE | |
| SN74F1056DR | ACTIVE | 0 to 70 | 4.25 | 1ku | SOIC (DW) | 16 | 2000 | LARGE T&R | |
| SN74F1056DRE4 | ACTIVE | 0 to 70 | 4.25 | 1ku | SOIC (DW) | 16 | 2000 | LARGE T&R | |
| SN74F1056DRG4 | ACTIVE | 0 to 70 | 4.25 | 1ku | SOIC (DW) | 16 | 2000 | LARGE T&R |
SN74F1056 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74F1056D | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F1056D | SN74F1056D |
| SN74F1056DE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F1056DE4 | SN74F1056DE4 |
| SN74F1056DG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F1056DG4 | SN74F1056DG4 |
| SN74F1056DR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F1056DR | SN74F1056DR |
| SN74F1056DRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F1056DRE4 | SN74F1056DRE4 |
| SN74F1056DRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F1056DRG4 | SN74F1056DRG4 |
SN74F1056 应用技术支持与电子电路设计开发资源下载
- SN74F1056 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)