SN74BCT8373A 具有八路寄存总线收发器的扫描测试设备
The 'BCT8373A scan test devices with octal D-type latches are members of the Texas Instruments SCOPETM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F373 and 'BCT373 octal D-type latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal latches
| SN74BCT8373A | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Logic | True |
| No. of Outputs | 8 |
| Output Drive(mA) | -15/64 |
| tpd max(ns) | 9.5 |
| Output Level | TTL |
| Static Current | 29.75 |
| Rating | Catalog |
| Technology Family | BCT |
SN74BCT8373A 特性
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Octal Test-Integrated Circuits
- Functionally Equivalent to 'F373 and 'BCT373 in the Normal-Function Mode
- Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
- Test Operation Synchronous to Test Access Port (TAP)
- Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V) on TMS Pin
- SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
- Parallel Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT)
SN74BCT8373A 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74BCT8373ADW | ACTIVE | 0 to 70 | 9.50 | 1ku | SOIC(DW) | 24 | 25 | TUBE | |
| SN74BCT8373ADWE4 | ACTIVE | 0 to 70 | 9.50 | 1ku | SOIC(DW) | 24 | 25 | TUBE | |
| SN74BCT8373ADWG4 | ACTIVE | 0 to 70 | 9.50 | 1ku | SOIC(DW) | 24 | 25 | TUBE |
SN74BCT8373A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74BCT8373ADW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74BCT8373ADW | SN74BCT8373ADW |
| SN74BCT8373ADWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74BCT8373ADWE4 | SN74BCT8373ADWE4 |
| SN74BCT8373ADWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74BCT8373ADWG4 | SN74BCT8373ADWG4 |
SN74BCT8373A 应用技术支持与电子电路设计开发资源下载
- SN74BCT8373A 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)