SN74AVCH8T245 具有可配置电压转换和 3 态输出的 8 位双电源总线收发器
This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH8T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH8T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.
The SN74AVCH8T245 is designed so the control pins (DIR and OE) are supplied by VCCA.
The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a '245 function, with minimal printed circuit board redesign.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
| SN74AVCH8T245 | |
| Vcc range(V) | 1.2 to 3.6 |
| Logic | True |
| No. of Bits | 8 |
| Bus Drive(ma) | -12/12 |
| Static Current | 0.025 |
| tpd max(ns) | 2.5 |
| Technology Family | AVC |
| Pin/Package | 24QFN, 24TSSOP, 24TVSOP |
| Operating Temperature Range(°C) | -40 to 85 |
| Approx. Price (US$) | 1.10 | 1ku |
| Rating | Catalog |
SN74AVCH8T245 特性
- Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
- VCC Isolation Feature — If Either VCC Input Is at GND, All I/O Ports Are in the High-Impedance State
- Ioff Supports Partial-Power-Down Mode Operation
- Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
- I/Os Are 4.6-V Tolerant
- Max Data Rates:
- 320 Mbps (VCCA ≤ 1.8 V and VCCB ≤ 1.8 V)
- 170 Mbps (VCCA ≥ 1.8 V or VCCB ≥ 1.8 V)
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 8000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74AVCH8T245 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74AVCH8T245PW | ACTIVE | -40 to 85 | 1.35 | 1ku | TSSOP (PW) | 24 | 60 | TUBE | |
| SN74AVCH8T245PWE4 | ACTIVE | -40 to 85 | 1.35 | 1ku | TSSOP (PW) | 24 | 60 | TUBE | |
| SN74AVCH8T245PWG4 | ACTIVE | -40 to 85 | 1.35 | 1ku | TSSOP (PW) | 24 | 60 | TUBE |
SN74AVCH8T245 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74AVCH8T245PW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AVCH8T245PW | SN74AVCH8T245PW |
| SN74AVCH8T245PWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AVCH8T245PWE4 | SN74AVCH8T245PWE4 |
| SN74AVCH8T245PWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AVCH8T245PWG4 | SN74AVCH8T245PWG4 |
SN74AVCH8T245 应用技术支持与电子电路设计开发资源下载
- SN74AVCH8T245 数据资料 dataSheet 下载.PDF
- TI 德州仪器电压电平转换产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)