SN74AUP1T157 低功耗、1.8/2.5/3.3V 输入、3.3V CMOS 输出、缓冲多路复用器（同向）
The SN74AUP1T157 is a single 2-input multiplexer that selects data from two data inputs (A and B) under control of a common data select input (C). The state of the common data select input determines the particular register from which the data comes. The output (Y) presents the selected data in the true (non-inverted) form.
AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 2 and Figure 3).
The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.
Schmitt-trigger inputs (
VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.
Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.
The SN74AUP1T157 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs
| SN74AUP1T157 | |
| tpd max(ns) | 10 |
| IOH(mA) | -4 |
| Vcc max(V) | 3.6 |
| Vcc min(V) | 2.3 |
| Operating Temperature Range(°C) | -40 to 85 |
| Technology Family | AUP |
| No. of Gates | 1 |
| ICC(uA) | 0.9 |
| Pin/Package | 6SC70 |
SN74AUP1T157 特性
- Single-Supply Voltage Translator
- Output Level Up to Supply VCC CMOS Level
- 1.8 V to 3.3 V (at VCC = 3.3 V)
- 2.5 V to 3.3 V (at VCC = 3.3 V)
- 1.8 V to 2.5 V (at VCC = 2.5 V)
- 3.3 V to 2.5 V (at VCC = 2.5 V
- Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity
- Ioff Supports Partial Power Down (VCC = 0 V)
- Very Low Static Power Consumption: 0.1 uA
- Very Low Dynamic Power Consumption: 0.9 uA
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- Pb-Free Packages Available: SC-70 (DCK) 2 x 2.1 x 0.65 mm (Height 1.1 mm)
- More Gate Options Available at www.ti.com/littlelogic
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
SN74AUP1T157 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74AUP1T157DCKR | ACTIVE | -40 to 85 | 0.10 | 1ku | SC70 (DCK) | 6 | 3000 | LARGE T&R |
SN74AUP1T157 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74AUP1T157DCKR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AUP1T157DCKR | SN74AUP1T157DCKR |
SN74AUP1T157 应用技术支持与电子电路设计开发资源下载
- SN74AUP1T157 数据资料 dataSheet 下载.PDF
- TI 德州仪器小尺寸逻辑器件产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)