SN74AUP1G17-EP 增强型产品低功耗单路施密特触发缓冲器

	SN74AUP1G17-EP
Pin/Package	5SC70
Operating Temperature Range(°C)	-55 to 125
Vcc max(V)	3.6
Technology Family	AUP
Vcc min(V)	0.8
ICC(uA)	0.5
Rating	HiRel Enhanced Product

SN74AUP1G17-EP 特性

• Controlled Baseline
  • One Assembly/Test Site, One Fabrication Site
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree(1)
• Available in the Texas Instruments NanoStarTM and NanoFreeTM Packages
• Low Static-Power Consumption (ICC = 0.9 uA Max)
• Low Dynamic-Power Consumption (Cpd = 4.4 pF Typ at 3.3 V)
• Low Input Capacitance (CI = 1.5 pF)
• Low Noise — Overshoot and Undershoot <10% of VCC
• Ioff Supports Partial-Power-Down Mode Operation
• Includes Schmitt-Trigger Inputs
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• tpd = 5.1 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model (A114-B, Class II)

SN74AUP1G17-EP 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74AUP1G17MDCKREP	ACTIVE	-55 to 125	0.95 | 1ku	SC70 (DCK) | 5	3000 | LARGE T&R
V62/07623-01XE	ACTIVE	-55 to 125	0.95 | 1ku	SC70 (DCK) | 5	3000 | LARGE T&R

SN74AUP1G17-EP 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74AUP1G17MDCKREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74AUP1G17MDCKREP	SN74AUP1G17MDCKREP
V62/07623-01XE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/07623-01XE	V62/07623-01XE

SN74AUP1G17-EP 应用技术支持与电子电路设计开发资源下载

1. SN74AUP1G17-EP 数据资料 dataSheet 下载.PDF
2. TI 德州仪器小尺寸逻辑器件产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)