SN74AS874 双路 4 位 D 类边沿触发器
These dual 4-bit D-type edge-triggered flip-flops feature 3-state outputs designed specifically as bus drivers. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The edge-triggered flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN54ALS874B, SN74ALS874B, and SN74AS874 have clear (
) inputs and noninverting Q outputs. The SN74ALS876A and SN74AS876 have preset (
) inputs and inverting Q\ outputs; taking low causes the four Q or Q\ outputs to go low independently of the clock.
The SN54ALS874B is characterized for operation over the full military temperature range of -55°C to 125°C
| SN74AS874 | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | TTL |
| Output Drive(mA) | -15/48 |
| No. of Outputs | 8 |
| Static Current | 141 |
| th(ns) | 1 |
| tpd max(ns) | 10.5 |
| tsu(ns) | 2 |
| Logic | True |
| Technology Family | AS |
| Rating | Catalog |
SN74AS874 特性
- 3-State Buffer-Type Outputs Drive Bus Lines Directly
- Bus-Structured Pinout
- Choice of True or Inverting Logic
- SN54ALS874B, SN74ALS874B, SN74AS874 Have True Outputs
- SN74ALS876A, SN74AS876 Have Inverting Outputs
- Asynchronous Clear
- Package Options Include Plastic Small-Outline (DW) Packages, Plastic (FN) and Ceramic (FK) Chip Carriers, and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN74AS874 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74AS874DW | ACTIVE | 0 to 70 | 1.10 | 1ku | SOIC(DW) | 24 | 25 | TUBE | AS874 |
| SN74AS874DWE4 | ACTIVE | 0 to 70 | 1.10 | 1ku | SOIC(DW) | 24 | 25 | TUBE | AS874 |
| SN74AS874DWG4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC(DW) | 24 | 2000 | LARGE T&R | AS874 |
| SN74AS874DWR | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC(DW) | 24 | 2000 | LARGE T&R | AS874 |
| SN74AS874DWRE4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC(DW) | 24 | 2000 | LARGE T&R | AS874 |
| SN74AS874DWRG4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC(DW) | 24 | 2000 | LARGE T&R | AS874 |
| SN74AS874N | ACTIVE | 0 to 70 | 1.00 | 1ku | PDIP (N) | 24 | 20 | TUBE | SN74AS874N |
| SN74AS874N3 | OBSOLETE | 0 to 70 | PDIP (N) | 24 | SN74AS874N | ||
| SN74AS874NE4 | ACTIVE | 0 to 70 | 1.00 | 1ku | PDIP (N) | 24 | 20 | TUBE | SN74AS874N |
| SN74AS874NSR | ACTIVE | 0 to 70 | 1.00 | 1ku | SO (NS) | 24 | 2000 | LARGE T&R | AS874 |
| SN74AS874NSRE4 | ACTIVE | 0 to 70 | 1.00 | 1ku | SO (NS) | 24 | 2000 | LARGE T&R | AS874 |
| SN74AS874NSRG4 | ACTIVE | 0 to 70 | 1.00 | 1ku | SO (NS) | 24 | 2000 | LARGE T&R | AS874 |
SN74AS874 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74AS874DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874DW | SN74AS874DW |
| SN74AS874DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874DWE4 | SN74AS874DWE4 |
| SN74AS874DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874DWG4 | SN74AS874DWG4 |
| SN74AS874DWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874DWR | SN74AS874DWR |
| SN74AS874DWRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874DWRE4 | SN74AS874DWRE4 |
| SN74AS874DWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874DWRG4 | SN74AS874DWRG4 |
| SN74AS874N | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874N | SN74AS874N |
| SN74AS874N3 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74AS874N3 | SN74AS874N3 |
| SN74AS874NE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74AS874NE4 | SN74AS874NE4 |
| SN74AS874NSR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874NSR | SN74AS874NSR |
| SN74AS874NSRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874NSRE4 | SN74AS874NSRE4 |
| SN74AS874NSRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS874NSRG4 | SN74AS874NSRG4 |
SN74AS874 应用技术支持与电子电路设计开发资源下载
- SN74AS874 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)