SN74AS194 4 位双向通用移位寄存器
These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation:
- Inhibit clock (temporary data latch/do nothing)
- Shift right (in the direction QA toward QD)
- Shift left (in the direction QD toward QA)
- Parallel (broadside) load
Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited
|
SN74AS194 |
| Technology Family |
AS |
| Rating |
Catalog |
SN74AS194 特性
- Parallel-to-Serial, Serial-to-Parallel Conversions
- Left or Right Shifts
- Parallel Synchronous Loading
- Direct Overriding Clear
- Temporary Data-Latching Capability
- Package Options Include Plastic Small-Outline Packages (D), Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN74AS194 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74AS194D |
ACTIVE |
0 to 70 |
0.65 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
ALS194 |
| SN74AS194DE4 |
ACTIVE |
0 to 70 |
0.65 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
ALS194 |
| SN74AS194DG4 |
ACTIVE |
0 to 70 |
0.65 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
ALS194 |
| SN74AS194DR |
ACTIVE |
0 to 70 |
0.55 | 1ku |
SOIC (DW) | 16 |
2500 | LARGE T&R |
ALS194 |
| SN74AS194DRE4 |
ACTIVE |
0 to 70 |
0.55 | 1ku |
SOIC (DW) | 16 |
2500 | LARGE T&R |
ALS194 |
| SN74AS194DRG4 |
ACTIVE |
0 to 70 |
0.55 | 1ku |
SOIC (DW) | 16 |
2500 | LARGE T&R |
ALS194 |
| SN74AS194N |
ACTIVE |
0 to 70 |
0.60 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
SN74AS194N |
| SN74AS194NE4 |
ACTIVE |
0 to 70 |
1.60 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
SN74AS194N |
SN74AS194 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74AS194D |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74AS194D |
SN74AS194D |
| SN74AS194DE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74AS194DE4 |
SN74AS194DE4 |
| SN74AS194DG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74AS194DG4 |
SN74AS194DG4 |
| SN74AS194DR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74AS194DR |
SN74AS194DR |
| SN74AS194DRE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74AS194DRE4 |
SN74AS194DRE4 |
| SN74AS194DRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74AS194DRG4 |
SN74AS194DRG4 |
| SN74AS194N |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
SN74AS194N |
SN74AS194N |
| SN74AS194NE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
SN74AS194NE4 |
SN74AS194NE4 |
SN74AS194 应用技术支持与电子电路设计开发资源下载
- SN74AS194 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)