SN74ALVTH16601 具有三态输出的 2.5V/3.3V 18 位通用总线收发器
The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB
| SN74ALVTH16601 | |
| Voltage Nodes(V) | 3.3, 2.5 |
| Rating | Catalog |
| Technology Family | ALVTLVT |
SN74ALVTH16601 特性
- UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
- State-of-the-Art Advanced BiCMOS Technology (ABT) WidebusTM Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- High-Drive (-24/24 mA at 2.5-V and -32/64 mA at 3.3-V VCC)
- Ioff and Power-Up 3-State Support Hot Insertion
- Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
- Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
- Flow-Through Architecture Facilitates Printed Circuit Board Layout
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
SN74ALVTH16601 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ALVTH16601DLG4 | ACTIVE | -40 to 85 | 4.30 | 1ku | SSOP (DL) | 56 | 20 | TUBE | |
| 74ALVTH16601DLRG4 | ACTIVE | -40 to 85 | 3.65 | 1ku | SSOP (DL) | 56 | 1000 | LARGE T&R | |
| 74ALVTH16601GRE4 | ACTIVE | -40 to 85 | 3.30 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| 74ALVTH16601GRG4 | ACTIVE | -40 to 85 | 3.30 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| 74ALVTH16601VRE4 | ACTIVE | -40 to 85 | 3.30 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R | |
| 74ALVTH16601VRG4 | ACTIVE | -40 to 85 | 3.30 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R | |
| SN74ALVTH16601DL | ACTIVE | -40 to 85 | 4.30 | 1ku | SSOP (DL) | 56 | 20 | TUBE | |
| SN74ALVTH16601DLR | ACTIVE | -40 to 85 | 3.65 | 1ku | SSOP (DL) | 56 | 1000 | LARGE T&R | |
| SN74ALVTH16601GR | ACTIVE | -40 to 85 | 3.30 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| SN74ALVTH16601VR | ACTIVE | -40 to 85 | 3.30 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R |
SN74ALVTH16601 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ALVTH16601DLG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16601DLG4 | 74ALVTH16601DLG4 |
| 74ALVTH16601DLRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16601DLRG4 | 74ALVTH16601DLRG4 |
| 74ALVTH16601GRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16601GRE4 | 74ALVTH16601GRE4 |
| 74ALVTH16601GRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16601GRG4 | 74ALVTH16601GRG4 |
| 74ALVTH16601VRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16601VRE4 | 74ALVTH16601VRE4 |
| 74ALVTH16601VRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16601VRG4 | 74ALVTH16601VRG4 |
| SN74ALVTH16601DL | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH16601DL | SN74ALVTH16601DL |
| SN74ALVTH16601DLR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH16601DLR | SN74ALVTH16601DLR |
| SN74ALVTH16601GR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH16601GR | SN74ALVTH16601GR |
| SN74ALVTH16601VR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH16601VR | SN74ALVTH16601VR |
SN74ALVTH16601 应用技术支持与电子电路设计开发资源下载
- SN74ALVTH16601 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)