SN74ALVTH16374 具有三态输出的 2.5V/3.3V 16 位边沿 D 类触发器
The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C.
The SN74ALVTH16374 is characterized for operation from -40°C to 85°C
| SN74ALVTH16374 | |
| Voltage Nodes(V) | 3.3, 2.5 |
| Technology Family | ALVC |
| Rating | Catalog |
SN74ALVTH16374 特性
- State-of-the-Art Advanced BiCMOSTechnology (ABT) WidebusTM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- High Drive (-24/24 mA at 2.5-V VCC and -32/64 mA at 3.3-V )
- Power Off Disables Outputs, Permitting Live Insertion
- High-Impedance State During Power Up and Power Down Prevents Driver Conflict
- Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
- Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection
- Exceeds 2000 V Per MIL-STD-883, Method 3015
- Exceeds 200 V Using Machine Model
- Exceeds 1000 V Using Charged-Device Model, Robotic Method
- Flow-Through Architecture Facilitates Printed Circuit Board Layout
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
SN74ALVTH16374 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ALVTH16374DGGRE4 | ACTIVE | -40 to 85 | 1.10 | 1ku | TSSOP (DGG) | 48 | 25 | TUBE | ALVCH16374 |
| 74ALVTH16374DGGRG4 | ACTIVE | -40 to 85 | 1.10 | 1ku | TSSOP (DGG) | 48 | 1000 | LARGE T&R | ALVCH16374 |
| 74ALVTH16374DGVRE4 | ACTIVE | -40 to 85 | 1.10 | 1ku | TVSOP (DGV) | 48 | 2000 | LARGE T&R | VH374 |
| 74ALVTH16374DGVRG4 | ACTIVE | -40 to 85 | 1.10 | 1ku | TVSOP (DGV) | 48 | 2000 | LARGE T&R | VH374 |
| 74ALVTH16374DLG4 | ACTIVE | -40 to 85 | 1.45 | 1ku | SSOP (DL) | 48 | 2000 | LARGE T&R | ALVCH16374 |
| 74ALVTH16374DLRG4 | ACTIVE | -40 to 85 | 1.25 | 1ku | SSOP (DL) | 48 | 2000 | LARGE T&R | ALVCH16374 |
| 74ALVTH16374ZQLR | ACTIVE | -40 to 85 | 1.65 | 1ku | BGA MICROSTAR JUNIOR (ZQL) | 48 | 1000 | LARGE T&R | VH374 |
| SN74ALVTH16374DGGR | ACTIVE | -40 to 85 | 1.10 | 1ku | TSSOP (DGG) | 48 | 25 | TUBE | ALVCH16374 |
| SN74ALVTH16374DGVR | ACTIVE | -40 to 85 | 1.10 | 1ku | TVSOP (DGV) | 48 | 1000 | LARGE T&R | ALVCH16374 |
| SN74ALVTH16374DL | ACTIVE | -40 to 85 | 1.45 | 1ku | SSOP (DL) | 48 | 2000 | LARGE T&R | ALVCH16374 |
| SN74ALVTH16374DLR | ACTIVE | -40 to 85 | 1.25 | 1ku | SSOP (DL) | 48 | 1000 | LARGE T&R | ALVCH16374 |
| SN74ALVTH16374KR | NRND | -40 to 85 | 1.65 | 1ku | BGA MICROSTAR JUNIOR (ZQL) | 48 | 2000 | LARGE T&R | VH374 |
SN74ALVTH16374 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ALVTH16374DGGRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16374DGGRE4 | 74ALVTH16374DGGRE4 |
| 74ALVTH16374DGGRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16374DGGRG4 | 74ALVTH16374DGGRG4 |
| 74ALVTH16374DGVRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16374DGVRE4 | 74ALVTH16374DGVRE4 |
| 74ALVTH16374DGVRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16374DGVRG4 | 74ALVTH16374DGVRG4 |
| 74ALVTH16374DLG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16374DLG4 | 74ALVTH16374DLG4 |
| 74ALVTH16374DLRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVTH16374DLRG4 | 74ALVTH16374DLRG4 |
| 74ALVTH16374ZQLR | Green (RoHS & no Sb/Br) | SNAGCU | Level-1-260C-UNLIM | 74ALVTH16374ZQLR | 74ALVTH16374ZQLR |
| SN74ALVTH16374DGGR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH16374DGGR | SN74ALVTH16374DGGR |
| SN74ALVTH16374DGVR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH16374DGVR | SN74ALVTH16374DGVR |
| SN74ALVTH16374DL | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH16374DL | SN74ALVTH16374DL |
| SN74ALVTH16374DLR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH16374DLR | SN74ALVTH16374DLR |
| SN74ALVTH16374KR | TBD | SNPB | Level-1-240C-UNLIM | SN74ALVTH16374KR | SN74ALVTH16374KR |
SN74ALVTH16374 应用技术支持与电子电路设计开发资源下载
- SN74ALVTH16374 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)