SN74ALVCH374 具有三态输出的八路上升沿 D 类触发器
This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components
| SN74ALVCH374 | |
| Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
| Technology Family | ALVC |
| Rating | Catalog |
SN74ALVCH374 特性
- Operates From 1.65 V to 3.6 V
- Max tpd of 3.6 ns at 3.3 V
- ±24-mA Output Drive at 3.3 V
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74ALVCH374 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ALVCH374DGVRE4 | ACTIVE | -40 to 85 | 0.55 | 1ku | TVSOP (DGV) | 20 | 2000 | LARGE T&R | |
| 74ALVCH374DGVRG4 | ACTIVE | -40 to 85 | 0.55 | 1ku | TVSOP (DGV) | 20 | 2000 | LARGE T&R | |
| SN74ALVCH374DGVR | ACTIVE | -40 to 85 | 0.55 | 1ku | TVSOP (DGV) | 20 | 2000 | LARGE T&R | |
| SN74ALVCH374DW | ACTIVE | -40 to 85 | 0.65 | 1ku | SOIC (DW) | 20 | 25 | TUBE | |
| SN74ALVCH374DWE4 | ACTIVE | -40 to 85 | 0.65 | 1ku | SOIC (DW) | 20 | 25 | TUBE | |
| SN74ALVCH374DWG4 | ACTIVE | -40 to 85 | 0.65 | 1ku | SOIC (DW) | 20 | 25 | TUBE | |
| SN74ALVCH374PW | ACTIVE | -40 to 85 | 0.65 | 1ku | TSSOP (PW) | 20 | 70 | TUBE | |
| SN74ALVCH374PWE4 | ACTIVE | -40 to 85 | 0.65 | 1ku | TSSOP (PW) | 20 | 70 | TUBE | |
| SN74ALVCH374PWG4 | ACTIVE | -40 to 85 | 0.65 | 1ku | TSSOP (PW) | 20 | 70 | TUBE | |
| SN74ALVCH374PWR | ACTIVE | -40 to 85 | 0.55 | 1ku | TSSOP (PW) | 20 | 2000 | LARGE T&R | |
| SN74ALVCH374PWRE4 | ACTIVE | -40 to 85 | 0.55 | 1ku | TSSOP (PW) | 20 | 2000 | LARGE T&R | |
| SN74ALVCH374PWRG4 | ACTIVE | -40 to 85 | 0.55 | 1ku | TSSOP (PW) | 20 | 2000 | LARGE T&R |
SN74ALVCH374 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ALVCH374DGVRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH374DGVRE4 | 74ALVCH374DGVRE4 |
| 74ALVCH374DGVRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH374DGVRG4 | 74ALVCH374DGVRG4 |
| SN74ALVCH374DGVR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374DGVR | SN74ALVCH374DGVR |
| SN74ALVCH374DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374DW | SN74ALVCH374DW |
| SN74ALVCH374DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374DWE4 | SN74ALVCH374DWE4 |
| SN74ALVCH374DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374DWG4 | SN74ALVCH374DWG4 |
| SN74ALVCH374PW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374PW | SN74ALVCH374PW |
| SN74ALVCH374PWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374PWE4 | SN74ALVCH374PWE4 |
| SN74ALVCH374PWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374PWG4 | SN74ALVCH374PWG4 |
| SN74ALVCH374PWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374PWR | SN74ALVCH374PWR |
| SN74ALVCH374PWRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374PWRE4 | SN74ALVCH374PWRE4 |
| SN74ALVCH374PWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH374PWRG4 | SN74ALVCH374PWRG4 |
SN74ALVCH374 应用技术支持与电子电路设计开发资源下载
- SN74ALVCH374 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)