SN74ALVCH16903 具有双路三态输出的 3.3V 12 位通用总线驱动器

This 12-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation.

The SN74ALVCH16903 has dual outputs and can operate as a buffer or an edge-triggered register. In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies. The YERR\ output, which is produced one cycle after APAR, is open drain.

MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered register. On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN\) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN\ is high, only data set up at the 9A-12A inputs is stored in their internal registers

	SN74ALVCH16903
Voltage Nodes(V)	3.3, 2.7, 2.5, 1.8
Rating	Catalog
Technology Family	ALVC

SN74ALVCH16903 特性

• EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
• Checks Parity
• Able to Cascade With a Second SN74ALVCH16903
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages

SN74ALVCH16903 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
74ALVCH16903DGGRE4	ACTIVE	-40 to 85	4.00 | 1ku	TSSOP (DGG) | 56	2000 | LARGE T&R
74ALVCH16903DGGRG4	ACTIVE	-40 to 85	4.00 | 1ku	TSSOP (DGG) | 56	2000 | LARGE T&R
74ALVCH16903DGVRE4	ACTIVE	-40 to 85	4.00 | 1ku	TVSOP (DGV) | 56	2000 | LARGE T&R
74ALVCH16903DGVRG4	ACTIVE	-40 to 85	4.00 | 1ku	TVSOP (DGV) | 56	2000 | LARGE T&R
74ALVCH16903DLG4	ACTIVE	-40 to 85	5.25 | 1ku	SSOP (DL) | 56	20 | TUBE
SN74ALVCH16903DGGR	ACTIVE	-40 to 85	4.00 | 1ku	TSSOP (DGG) | 56	2000 | LARGE T&R
SN74ALVCH16903DGVR	ACTIVE	-40 to 85	4.00 | 1ku	TVSOP (DGV) | 56	2000 | LARGE T&R
SN74ALVCH16903DL	ACTIVE	-40 to 85	5.25 | 1ku	SSOP (DL) | 56	20 | TUBE

SN74ALVCH16903 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
74ALVCH16903DGGRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ALVCH16903DGGRE4	74ALVCH16903DGGRE4
74ALVCH16903DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ALVCH16903DGGRG4	74ALVCH16903DGGRG4
74ALVCH16903DGVRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ALVCH16903DGVRE4	74ALVCH16903DGVRE4
74ALVCH16903DGVRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ALVCH16903DGVRG4	74ALVCH16903DGVRG4
74ALVCH16903DLG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ALVCH16903DLG4	74ALVCH16903DLG4
SN74ALVCH16903DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ALVCH16903DGGR	SN74ALVCH16903DGGR
SN74ALVCH16903DGVR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ALVCH16903DGVR	SN74ALVCH16903DGVR
SN74ALVCH16903DL	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ALVCH16903DL	SN74ALVCH16903DL

SN74ALVCH16903 应用技术支持与电子电路设计开发资源下载

1. SN74ALVCH16903 数据资料 dataSheet 下载.PDF
2. TI 德州仪器通用总线功能产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)