SN74ALVCH16901 具有奇偶校验发生器/校验器的 18 位通用总线收发器
This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.
The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB\ or CLKENBA\) inputs. It also provides parity-enable (SEL\) and parity-select (ODD/EVEN\) inputs and separate error-signal (ERRA\ or ERRB\) outputs for checking parity. The direction of data flow is controlled by OEAB\ and OEBA\. When SEL\ is low, the parity functions are enabled
| SN74ALVCH16901 | |
| Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
| Vcc range(V) | 1.65 to 3.6 |
| Input Level | LVTTL |
| Output Level | LVTTL |
| Output Drive(mA) | -24/24 |
| No. of Outputs | 18 |
| Logic | True |
| Static Current | 0.04 |
| tpd max(ns) | 4.4 |
| Rating | Catalog |
| Technology Family | ALVC |
SN74ALVCH16901 特性
- Member of the Texas Instruments Widebus+TM Family
- UBTTM Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
- Operates From 1.65 V to 3.6 V
- Max tpd of 4.4 ns at 3.3 V
- ±24-mA Output Drive at 3.3 V
- Simultaneously Generates and Checks Parity
- Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
SN74ALVCH16901 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ALVCH16901DGGRE4 | ACTIVE | -40 to 85 | 3.30 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| 74ALVCH16901DGGRG4 | ACTIVE | -40 to 85 | 3.30 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| SN74ALVCH16901DGGR | ACTIVE | -40 to 85 | 3.30 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R |
SN74ALVCH16901 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ALVCH16901DGGRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16901DGGRE4 | 74ALVCH16901DGGRE4 |
| 74ALVCH16901DGGRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16901DGGRG4 | 74ALVCH16901DGGRG4 |
| SN74ALVCH16901DGGR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH16901DGGR | SN74ALVCH16901DGGR |
SN74ALVCH16901 应用技术支持与电子电路设计开发资源下载
- SN74ALVCH16901 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)