SN74ALVCH16835 具有三态输出的 18 位通用总线驱动器
This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state
| SN74ALVCH16835 | |
| Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
| Rating | Catalog |
| Technology Family | ALVC |
SN74ALVCH16835 特性
- Member of the Texas Instruments WidebusTM Family
- Operates From 1.65 V to 3.6 V
- Max tpd of 3.6 ns at 3.3 V
- ±24-mA Output Drive at 3.3 V
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
SN74ALVCH16835 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ALVCH16835DGGRE4 | ACTIVE | -40 to 85 | 4.00 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| 74ALVCH16835DGGRG4 | ACTIVE | -40 to 85 | 4.00 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| 74ALVCH16835DGVRE4 | ACTIVE | -40 to 85 | 4.00 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R | |
| 74ALVCH16835DGVRG4 | ACTIVE | -40 to 85 | 4.00 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R | |
| 74ALVCH16835DLG4 | ACTIVE | -40 to 85 | 5.25 | 1ku | SSOP (DL) | 56 | 20 | TUBE | |
| SN74ALVCH16835DGGR | ACTIVE | -40 to 85 | 4.00 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| SN74ALVCH16835DGVR | ACTIVE | -40 to 85 | 4.00 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R | |
| SN74ALVCH16835DL | ACTIVE | -40 to 85 | 5.25 | 1ku | SSOP (DL) | 56 | 20 | TUBE |
SN74ALVCH16835 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ALVCH16835DGGRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16835DGGRE4 | 74ALVCH16835DGGRE4 |
| 74ALVCH16835DGGRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16835DGGRG4 | 74ALVCH16835DGGRG4 |
| 74ALVCH16835DGVRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16835DGVRE4 | 74ALVCH16835DGVRE4 |
| 74ALVCH16835DGVRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16835DGVRG4 | 74ALVCH16835DGVRG4 |
| 74ALVCH16835DLG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16835DLG4 | 74ALVCH16835DLG4 |
| SN74ALVCH16835DGGR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH16835DGGR | SN74ALVCH16835DGGR |
| SN74ALVCH16835DGVR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH16835DGVR | SN74ALVCH16835DGVR |
| SN74ALVCH16835DL | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH16835DL | SN74ALVCH16835DL |
SN74ALVCH16835 应用技术支持与电子电路设计开发资源下载
- SN74ALVCH16835 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)