SN74ALVCH16500 具有三态输出的 18 位通用总线收发器

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

Data flow in each direction is controlled by output-enable (OEAB and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB\ and CLKBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\ is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\. Output-enable OEAB is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, and CLKBA\

	SN74ALVCH16500
Voltage Nodes(V)	3.3, 2.7, 2.5, 1.8
Vcc range(V)	1.65 to 3.6
Input Level	LVTTL
Output Level	LVTTL
Output Drive(mA)	-24/24
No. of Outputs	18
Logic	True
Static Current	0.04
tpd max(ns)	3.9
Rating	Catalog
Technology Family	ALVC

SN74ALVCH16500 特性

• Member of the Texas Instruments WidebusTM Family
• EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
• UBTTM (Universal Bus Transceiver) Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

SN74ALVCH16500 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
74ALVCH16500DGGRE4	ACTIVE	-40 to 85	1.21 | 1ku	TSSOP (DGG) | 56	2000 | LARGE T&R
74ALVCH16500DGGRG4	ACTIVE	-40 to 85	1.21 | 1ku	TSSOP (DGG) | 56	2000 | LARGE T&R
74ALVCH16500DLG4	ACTIVE	-40 to 85	1.21 | 1ku	SSOP (DL) | 56	20 | TUBE
74ALVCH16500DLRG4	ACTIVE	-40 to 85	1.21 | 1ku	SSOP (DL) | 56	1000 | LARGE T&R
SN74ALVCH16500DGGR	ACTIVE	-40 to 85	1.21 | 1ku	TSSOP (DGG) | 56	2000 | LARGE T&R
SN74ALVCH16500DL	ACTIVE	-40 to 85	1.21 | 1ku	SSOP (DL) | 56	20 | TUBE
SN74ALVCH16500DLR	ACTIVE	-40 to 85	1.21 | 1ku	SSOP (DL) | 56	1000 | LARGE T&R

SN74ALVCH16500 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
74ALVCH16500DGGRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ALVCH16500DGGRE4	74ALVCH16500DGGRE4
74ALVCH16500DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ALVCH16500DGGRG4	74ALVCH16500DGGRG4
74ALVCH16500DLG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ALVCH16500DLG4	74ALVCH16500DLG4
74ALVCH16500DLRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ALVCH16500DLRG4	74ALVCH16500DLRG4
SN74ALVCH16500DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ALVCH16500DGGR	SN74ALVCH16500DGGR
SN74ALVCH16500DL	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ALVCH16500DL	SN74ALVCH16500DL
SN74ALVCH16500DLR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ALVCH16500DLR	SN74ALVCH16500DLR

SN74ALVCH16500 应用技术支持与电子电路设计开发资源下载

1. SN74ALVCH16500 数据资料 dataSheet 下载.PDF
2. TI 德州仪器通用总线功能产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)