SN74ALVCH16271 具有三态输出的 12 位到 24 位多路复用总线交换器
This 12-bit to 24-bit bus exchanger is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16271 is intended for applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. This device is particularly suitable as an interface between conventional DRAMs and high-speed microprocessors.
A data is stored in the internal A-to-B registers on the low-to-high transition of the clock (CLK) input, provided that the clock-enable (CLKENA\) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port.
Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput
| SN74ALVCH16271 | |
| Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
| Vcc range(V) | 1.65 to 3.6 |
| Input Level | LVTTL |
| Output Level | LVTTL |
| Output Drive(mA) | -24/24 |
| No. of Outputs | 12 |
| Logic | True |
| Static Current | 0.04 |
| Rating | Catalog |
| Technology Family | ALVC |
SN74ALVCH16271 特性
- Member of Texas Instruments WidebusTMFamily
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
SN74ALVCH16271 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ALVCH16271DLG4 | ACTIVE | -40 to 85 | 1.75 | 1ku | SSOP (DL) | 56 | 20 | TUBE | |
| 74ALVCH16271GRE4 | ACTIVE | -40 to 85 | 1.35 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| 74ALVCH16271GRG4 | ACTIVE | -40 to 85 | 1.35 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| SN74ALVCH16271DL | ACTIVE | -40 to 85 | 1.75 | 1ku | SSOP (DL) | 56 | 20 | TUBE | |
| SN74ALVCH16271GR | ACTIVE | -40 to 85 | 1.35 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| SN74ALVCH16271KR | NRND | -40 to 85 | 2.05 | 1ku | BGA MICROSTAR JUNIOR (GQL) | 56 | 1000 | LARGE T&R |
SN74ALVCH16271 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ALVCH16271DLG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16271DLG4 | 74ALVCH16271DLG4 |
| 74ALVCH16271GRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16271GRE4 | 74ALVCH16271GRE4 |
| 74ALVCH16271GRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVCH16271GRG4 | 74ALVCH16271GRG4 |
| SN74ALVCH16271DL | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH16271DL | SN74ALVCH16271DL |
| SN74ALVCH16271GR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVCH16271GR | SN74ALVCH16271GR |
| SN74ALVCH16271KR | TBD | SNPB | Level-1-240C-UNLIM | SN74ALVCH16271KR | SN74ALVCH16271KR |
SN74ALVCH16271 应用技术支持与电子电路设计开发资源下载
- SN74ALVCH16271 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)