SN74ALVC7805 256 x 18 3.3V 同步 FIFO 存储器
The SN74ALVC7805 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels
|
SN74ALVC7805 |
| Depth |
256 |
| Width |
18 |
| Fmax(MHz) |
50 |
| Sync/Async |
S |
| Voltage Nodes(V) |
3.3 |
| Vcc range(V) |
3.0 to 3.6 |
| Technology Family |
ALVC |
| Output Drive(mA) |
-8/16 |
| Rating |
Catalog |
SN74ALVC7805 特性
- Member of the Texas Instruments WidebusTM Family
- Low-Power Advanced CMOS Technology
- Operates From 3-V to 3.6-V VCC
- Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
- Read and Write Operations Synchronized to Independent System Clocks
- Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
- Bidirectional Configuration and Width Expansion Without Additional Logic
- Input-Ready Flag Synchronized to Write Clock
- Output-Ready Flag Synchronized to Read Clock
- Fast Access Times of 13 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
- Data Rates up to 50 MHz
- Pin-to-Pin Compatible With SN74ACT7803, SN74ACT7805, and SN74ACT7813
- Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Lead Spacing
SN74ALVC7805 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74ALVC7805-20DL |
ACTIVE |
0 to 70 |
11.94 | 1ku |
SSOP (DL) | 56 |
20 | TUBE |
|
| SN74ALVC7805-25DL |
ACTIVE |
0 to 70 |
5.27 | 1ku |
SSOP (DL) | 56 |
20 | TUBE |
|
| SN74ALVC7805-40DL |
ACTIVE |
0 to 70 |
3.95 | 1ku |
SSOP (DL) | 56 |
20 | TUBE |
|
| SN74ALVC7805-40DLR |
ACTIVE |
0 to 70 |
7.48 | 1ku |
SSOP (DL) | 56 |
1000 | LARGE T&R |
|
SN74ALVC7805 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74ALVC7805-20DL |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74ALVC7805-20DL |
SN74ALVC7805-20DL |
| SN74ALVC7805-25DL |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74ALVC7805-25DL |
SN74ALVC7805-25DL |
| SN74ALVC7805-40DL |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74ALVC7805-40DL |
SN74ALVC7805-40DL |
| SN74ALVC7805-40DLR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74ALVC7805-40DLR |
SN74ALVC7805-40DLR |
SN74ALVC7805 应用技术支持与电子电路设计开发资源下载
- SN74ALVC7805 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)