SN74ALVC162334 具有三态输出的 16 位通用总线驱动器
This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-
resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
| SN74ALVC162334 | |
| Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
| Rating | Catalog |
| Technology Family | ALVC |
SN74ALVC162334 特性
- Member of the Texas Instruments WidebusTM Family
- Ideal for Use in PC100 Register DIMM
- Operates From 1.65 V to 3.6 V
- Max tpd of 3.8 ns at 3.3 V
- ±12-mA Output Drive at 3.3 V
- Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
- Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74ALVC162334 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ALVC162334DGGRE4 | ACTIVE | -40 to 85 | 3.63 | 1ku | TSSOP (DGG) | 48 | 2000 | LARGE T&R | |
| 74ALVC162334DGGRG4 | ACTIVE | -40 to 85 | 3.63 | 1ku | TSSOP (DGG) | 48 | 2000 | LARGE T&R | |
| 74ALVC162334DGVRE4 | ACTIVE | -40 to 85 | 3.63 | 1ku | TVSOP (DGV) | 48 | 2000 | LARGE T&R | |
| 74ALVC162334DGVRG4 | ACTIVE | -40 to 85 | 3.63 | 1ku | TVSOP (DGV) | 48 | 2000 | LARGE T&R | |
| 74ALVC162334DLG4 | ACTIVE | -40 to 85 | 3.63 | 1ku | SSOP (DL) | 48 | 25 | TUBE | |
| 74ALVC162334DLRG4 | ACTIVE | -40 to 85 | 3.63 | 1ku | SSOP (DL) | 48 | 1000 | LARGE T&R | |
| SN74ALVC162334DGGR | ACTIVE | -40 to 85 | 3.63 | 1ku | TSSOP (DGG) | 48 | 2000 | LARGE T&R | |
| SN74ALVC162334DGVR | ACTIVE | -40 to 85 | 3.63 | 1ku | TVSOP (DGV) | 48 | 2000 | LARGE T&R | |
| SN74ALVC162334DL | ACTIVE | -40 to 85 | 3.63 | 1ku | SSOP (DL) | 48 | 25 | TUBE | |
| SN74ALVC162334DLR | ACTIVE | -40 to 85 | 3.63 | 1ku | SSOP (DL) | 48 | 1000 | LARGE T&R |
SN74ALVC162334 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ALVC162334DGGRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVC162334DGGRE4 | 74ALVC162334DGGRE4 |
| 74ALVC162334DGGRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVC162334DGGRG4 | 74ALVC162334DGGRG4 |
| 74ALVC162334DGVRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVC162334DGVRE4 | 74ALVC162334DGVRE4 |
| 74ALVC162334DGVRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVC162334DGVRG4 | 74ALVC162334DGVRG4 |
| 74ALVC162334DLG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVC162334DLG4 | 74ALVC162334DLG4 |
| 74ALVC162334DLRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ALVC162334DLRG4 | 74ALVC162334DLRG4 |
| SN74ALVC162334DGGR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVC162334DGGR | SN74ALVC162334DGGR |
| SN74ALVC162334DGVR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVC162334DGVR | SN74ALVC162334DGVR |
| SN74ALVC162334DL | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVC162334DL | SN74ALVC162334DL |
| SN74ALVC162334DLR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVC162334DLR | SN74ALVC162334DLR |
SN74ALVC162334 应用技术支持与电子电路设计开发资源下载
- SN74ALVC162334 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
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- Logic Cross-Reference (PDF 2938 KB)