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SN74AHCT74-EP 具有清零和预设功能的双路上升沿 D 类触发器

The SN74AHCT74 is a dual positive-edge-triggered D-type flip-flop.

A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs

SN74AHCT74-EP
Voltage Nodes(V) 5, 3.3
Rating Catalog
SN74AHCT74-EP 特性
SN74AHCT74-EP 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74AHCT74MDREP ACTIVE -55 to 125 0.70 | 1ku SOIC (D) | 14 2500 | LARGE T&R  
V62/04617-01XE ACTIVE -55 to 125 0.70 | 1ku SOIC (D) | 14 2500 | LARGE T&R  
SN74AHCT74-EP 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74AHCT74MDREP Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT74MDREP SN74AHCT74MDREP
V62/04617-01XE Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04617-01XE V62/04617-01XE
SN74AHCT74-EP 应用技术支持与电子电路设计开发资源下载
  1. SN74AHCT74-EP 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
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  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)