SN74ABTH32501 具有三态输出的 36 位通用总线收发器

These 36-bit UBTs combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, and CLKBA.

Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state

	SN74ABTH32501
Voltage Nodes(V)	5
Rating	Catalog
Technology Family	ABT

SN74ABTH32501 特性

• Members of the Texas Instruments Widebus+TM Family
• State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
• UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Released as DSCC SMD 5962-9557601NXD
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
• High-Impedance State During Power Up and Power Down
• Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
• High-Drive Outputs (-32-mA IOH, 64-mA IOL)
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 × 14-mm Body Using 0.5-mm Lead Pitch and Space-Saving 100-Pin Ceramic Quad Flat (HS) Package

SN74ABTH32501 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74ABTH32501PZ	ACTIVE	-40 to 85	19.80 | 1ku	LQFP (PZ) | 100	90 | JEDEC TRAY (5+1)
SN74ABTH32501PZG4	ACTIVE	-40 to 85	19.80 | 1ku	LQFP (PZ) | 100	90 | JEDEC TRAY (5+1)

SN74ABTH32501 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74ABTH32501PZ	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	SN74ABTH32501PZ	SN74ABTH32501PZ
SN74ABTH32501PZG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	SN74ABTH32501PZG4	SN74ABTH32501PZG4

SN74ABTH32501 应用技术支持与电子电路设计开发资源下载

1. SN74ABTH32501 数据资料 dataSheet 下载.PDF
2. TI 德州仪器通用总线功能产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)