SN74ABTH32318 16 位三端口通用总线交换器
The 'ABTH32318 consist of three 18-bit registered input/output (I/O) ports. These registers combine D-type latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations of real-time and stored data can be exchanged among the three ports.
Data flow in each direction is controlled by the output-enable (OEA\, OEB\, and OEC\), select-control (SELA, SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held at a high or low logic level
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SN74ABTH32318 |
| Voltage Nodes(V) |
5 |
| Rating |
Catalog |
| Technology Family |
ABT |
SN74ABTH32318 特性
- Members of the Texas Instruments Widebus+TM Family
- State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
- UBETM (Universal Bus Exchanger) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
- High-Impedance State During Power Up and Power Down
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- High-Drive Outputs (-32-mA IOH, 64-mA IOL)
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Package Options Include 80-Pin Plastic Thin Quad Flat (PN) Package With 12 × 12-mm Body Using 0.5-mm Lead Pitch and 84-Pin Ceramic Quad Flat (HT) Package
SN74ABTH32318 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74ABTH32318PN |
ACTIVE |
-40 to 85 |
22.80 | 1ku |
LQFP (PN) | 80 |
119 | JEDEC TRAY (10+1) |
|
| SN74ABTH32318PNG4 |
ACTIVE |
-40 to 85 |
22.80 | 1ku |
LQFP (PN) | 80 |
119 | JEDEC TRAY (10+1) |
|
SN74ABTH32318 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74ABTH32318PN |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74ABTH32318PN |
SN74ABTH32318PN |
| SN74ABTH32318PNG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74ABTH32318PNG4 |
SN74ABTH32318PNG4 |
SN74ABTH32318 应用技术支持与电子电路设计开发资源下载
- SN74ABTH32318 数据资料 dataSheet 下载.PDF
- TI 德州仪器通用总线功能产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)