SN74ABTH32316 16 位三端口通用总线交换器

The 'ABTH32316 consist of three 16-bit registered input/output (I/O) ports. These registers combine D-type latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations of real-time and stored data can be exchanged among the three ports.

Data flow in each direction is controlled by the output-enable (OEA\, OEB\, and OEC\), select-control (SELA, SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held at a high or low logic level.

	SN74ABTH32316
Voltage Nodes(V)	5
Rating	Catalog
Technology Family	ABT

SN74ABTH32316 特性

• Members of the Texas Instruments Widebus+TM Family
• State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
• UBETM (Universal Bus Exchanger) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
• High-Impedance State During Power Up and Power Down
• Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
• High-Drive Outputs (-32-mA IOH, 64-mA IOL)
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include 80-Pin Plastic Thin Quad Flat (PN) Package With 12 × 12-mm Body Using 0.5-mm Lead Pitch and 84-Pin Ceramic Quad Flat (HT) Package

SN74ABTH32316 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74ABTH32316PN	ACTIVE	-40 to 85	22.80 | 1ku	LQFP (PN) | 80	119 | JEDEC TRAY (10+1)
SN74ABTH32316PNG4	ACTIVE	-40 to 85	22.80 | 1ku	LQFP (PN) | 80	119 | JEDEC TRAY (10+1)

SN74ABTH32316 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74ABTH32316PN	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	SN74ABTH32316PN	SN74ABTH32316PN
SN74ABTH32316PNG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-3-260C-168 HR	SN74ABTH32316PNG4	SN74ABTH32316PNG4

SN74ABTH32316 应用技术支持与电子电路设计开发资源下载

1. SN74ABTH32316 数据资料 dataSheet 下载.PDF
2. TI 德州仪器通用总线功能产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)