SN74ABT8996 10 位可寻址扫描端口，多点可寻址 IEEE 标准 1194.1 (JTAG) TAP 收发器

The 'ABT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments (TITM) SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETM devices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Standard 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.

Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP

	SN74ABT8996
Voltage Nodes(V)	5
Vcc range(V)	4.5 to 5.5
Input Level	TTL
Output Level	TTL
Rating	Catalog
Technology Family	JTAG

SN74ABT8996 特性

• Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
• Extend Scan Access From Board Level to Higher Levels of System Integration
• Promote Reuse of Lower-Level (Chip/Board) Tests in System Environment
• Switch-Based Architecture Allows Direct Connect of Primary TAP to Secondary TAP
• Primary TAP Is Multidrop for Minimal Use of Backplane Wiring Channels
• Simple Addressing (Shadow) Protocol Is Received/Acknowledged on Primary TAP
• Shadow Protocols Can Occur in Any of Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR TAP States to Provide for Board-to-Board Test and Built-In Self-Test
• 10-Bit Address Space Provides for Up to 1021 User-Specified Board Addresses
• Bypass (BYP\) Pin Forces Primary-to-Secondary Connection Without Use of Shadow Protocols
• Connect (CON\) Pin Provides Indication of Primary-to-Secondary Connection
• High-Drive Outputs (-32-mA IOH, 64-mA IOL) Support Backplane Interface at Primary and High Fanout at Secondary
• Package Options Include Plastic Small- Outline (DW) and Thin Shrink Small- Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic DIPs (JT)

SN74ABT8996 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74ABT8996DW	ACTIVE	-40 to 85	7.15 | 1ku	SOIC (DW) | 24	25 | TUBE
SN74ABT8996DWR	ACTIVE	-40 to 85	7.15 | 1ku	SOIC (DW) | 24	2000 | LARGE T&R

SN74ABT8996 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74ABT8996DW	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ABT8996DW	SN74ABT8996DW
SN74ABT8996DWR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ABT8996DWR	SN74ABT8996DWR

SN74ABT8996 应用技术支持与电子电路设计开发资源下载

1. SN74ABT8996 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)