SN74ABT16841 具有三态输出的 20 位总线接口 D 类锁存器
These 20-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The 'ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state
|
SN74ABT16841 |
| Voltage Nodes(V) |
5 |
| Technology Family |
ABT |
| Rating |
Catalog |
SN74ABT16841 特性
- Members of the Texas Instruments WidebusTM Family
- State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
- High-Impedance State During Power Up and Power Down
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- High-Drive Outputs (-32-mA IOH, 64-mA IOL)
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN74ABT16841 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74ABT16841DGGR |
ACTIVE |
-40 to 85 |
2.64 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
| SN74ABT16841DL |
ACTIVE |
-40 to 85 |
2.64 | 1ku |
SSOP (DL) | 56 |
20 | TUBE |
|
| SN74ABT16841DLG4 |
ACTIVE |
-40 to 85 |
2.64 | 1ku |
SSOP (DL) | 56 |
20 | TUBE |
|
| SN74ABT16841DLR |
ACTIVE |
-40 to 85 |
2.64 | 1ku |
SSOP (DL) | 56 |
1000 | LARGE T&R |
|
SN74ABT16841 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74ABT16841DGGR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74ABT16841DGGR |
SN74ABT16841DGGR |
| SN74ABT16841DL |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74ABT16841DL |
SN74ABT16841DL |
| SN74ABT16841DLG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74ABT16841DLG4 |
SN74ABT16841DLG4 |
| SN74ABT16841DLR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74ABT16841DLR |
SN74ABT16841DLR |
SN74ABT16841 应用技术支持与电子电路设计开发资源下载
- SN74ABT16841 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)