SN74ABT162601 具有三态输出的 18 位通用总线收发器

These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs.

For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB\ is active-low. When OEAB\ is low, the outputs are active

	SN74ABT162601
Voltage Nodes(V)	5
Vcc range(V)	4.5 to 5.5
Input Level	TTL
Output Level	TTL
Output Drive(mA)	-32/64
No. of Outputs	18
Logic	True
Static Current	19.5
tpd max(ns)	5.7
Rating	Catalog
Technology Family	ABT

SN74ABT162601 特性

Members of the Texas Instruments WidebusTM Family
B-Port Outputs Have Equivalent 25- Series Resistors, So No External Resistors Are Required
State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
Latch-Up Performance Exceeds 500 mA Per JESD 17
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
High-Impedance State During Power Up and Power Down
Flow-Through Architecture Optimizes PCB Layout
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

SN74ABT162601 芯片订购指南

器件	状态	温度	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体	丝印标记
74ABT162601DGGRE4	ACTIVE	-40 to 85	3.85 \| 1ku	TSSOP (DGG) \| 56	2000 \| LARGE T&R
74ABT162601DGGRG4	ACTIVE	-40 to 85	3.85 \| 1ku	TSSOP (DGG) \| 56	2000 \| LARGE T&R
74ABT162601DLRG4	ACTIVE	-40 to 85	4.25 \| 1ku	SSOP (DL) \| 56	1000 \| LARGE T&R
SN74ABT162601DGGR	ACTIVE	-40 to 85	3.85 \| 1ku	TSSOP (DGG) \| 56	2000 \| LARGE T&R
SN74ABT162601DL	ACTIVE	-40 to 85	5.05 \| 1ku	SSOP (DL) \| 56	20 \| TUBE
SN74ABT162601DLG4	ACTIVE	-40 to 85	5.05 \| 1ku	SSOP (DL) \| 56	20 \| TUBE
SN74ABT162601DLR	ACTIVE	-40 to 85	4.25 \| 1ku	SSOP (DL) \| 56	1000 \| LARGE T&R

SN74ABT162601 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
74ABT162601DGGRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ABT162601DGGRE4	74ABT162601DGGRE4
74ABT162601DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ABT162601DGGRG4	74ABT162601DGGRG4
74ABT162601DLRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	74ABT162601DLRG4	74ABT162601DLRG4
SN74ABT162601DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ABT162601DGGR	SN74ABT162601DGGR
SN74ABT162601DL	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ABT162601DL	SN74ABT162601DL
SN74ABT162601DLG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ABT162601DLG4	SN74ABT162601DLG4
SN74ABT162601DLR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74ABT162601DLR	SN74ABT162601DLR

SN74ABT162601 应用技术支持与电子电路设计开发资源下载

SN74ABT162601 数据资料 dataSheet 下载.PDF
TI 德州仪器通用总线功能产品选型与价格 . xls
Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
CMOS Power Consumption and CPD Calculation (PDF 89 KB)
Designing With Logic (PDF 186 KB)
Live Insertion (PDF 150 KB)
Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
HiRel Unitrode Power Management Brochure (PDF 206 KB)
LOGIC Pocket Data Book (PDF 6001 KB)
HiRel Unitrode Power Management Brochure (PDF 206 KB)
Logic Cross-Reference (PDF 2938 KB)