SN65LVDT3486B 具有 -2 至 4.4V 常见模式范围的四路 LVDS 接收器
Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver
SN65LVDT3486B
Input Signal
LVDS
Output Signal
LVTTL
No. of Rx
4
Signaling Rate(Mbps)
400
Supply Voltage(s)(V)
3.3
ICC(Max)(mA)
23
Rx tpd(Typ)(ns)
4
Part-to-Part Skew(Max)(ps)
1000
Pin/Package
16SOIC
Operating Temperature Range(°C)
-40 to 85
ESD HBM(kV)
15
Approx. Price (US$)
2.45 | 1ku
SN65LVDT3486B 特性
Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard for Signaling Rates(1) up to 400 Mbps
Operates With a Single 3.3-V Supply
-2-V to 4.4-V Common-Mode Input Voltage Range
Differential Input Thresholds <50 mV With 50 mV of Hysteresis Over Entire Common-
Mode Input Voltage Range
Integrated 110- Propagation Delay Times 4 ns (typ)
Active Fail Safe Assures a High-Level Output With No Input
Bus-Pin ESD Protection Exceeds 15 kV—HBM
Inputs Remain High-Impedance on Power Down
Recommended Maximum Parallel Rate of 200 M-Transfer/s
Available in Small-Outline Package With 1,27-mm Terminal Pitch
Pin-Compatible With the AM26LS32, MC3486, or uA9637
SN65LVDT3486B 芯片订购指南
器件
状态
温度
价格
封装 | 引脚
封装数量 | 封装载体
丝印标记
SN65LVDT3486BD
ACTIVE
-40 to 85
1.45 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDT3486BDG4
ACTIVE
-40 to 85
1.45 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDT3486BDR
ACTIVE
-40 to 85
1.20 | 1ku
SOIC (D) | 16 2500 | LARGE T&R
SN65LVDT3486BDRG4
ACTIVE
-40 to 85
1.20 | 1ku
SOIC (D) | 16 2500 | LARGE T&R
SN65LVDT3486B 质量与无铅数据
器件
环保计划*
铅/焊球涂层
MSL 等级/回流焊峰
环保信息与无铅 (Pb-free)
DPPM / MTBF / FIT 率
SN65LVDT3486BD
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT3486BD
SN65LVDT3486BD
SN65LVDT3486BDG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT3486BDG4 SN65LVDT3486BDG4
SN65LVDT3486BDR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT3486BDR
SN65LVDT3486BDR
SN65LVDT3486BDRG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT3486BDRG4 SN65LVDT3486BDRG4
SN65LVDT3486B 应用技术支持与电子电路设计开发资源下载
SN65LVDT3486B 数据资料 dataSheet 下载 .PDF TI 德州仪器LVDS PHYs选型与价格 . xls 所选封装材料的热学和电学性质 (PDF 645 KB)使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)接口选择指南 (Rev. D) (PDF 2994 KB)Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)Isolated RS-485 Reference Design (PDF 80 KB)无铅组件涂层的保存期评估 (PDF 1305 KB)Analog Signal Chain Guide (8.62 MB)Industrial Interface IC Solutions (101 KB)
This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers.
Line Termination Resistors Offered With the LVDT Series