SN65LVDS9637 双路 LVDS 接收器

The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.

The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100

	SN65LVDS34	SN65LVDS9637	SN65LVDS9638
Input Signal	CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL	LVDS	LVTTL
Output Signal	LVTTL	LVTTL	LVDS
No. of Rx	2	2
No. of Tx			2
Signaling Rate(Mbps)	400	150	150
Supply Voltage(s)(V)	3.3	3.3	3.3
ICC(Max)(mA)	12	10	13
Rx tpd(Typ)(ns)	4	2.1
Tx tpd(Typ)(ns)			1.7
Part-to-Part Skew(Max)(ps)	1000	1000	800
Pin/Package	8SOIC	8MSOP, 8MSOP-PowerPAD, 8SOIC	8MSOP, 8MSOP-PowerPAD, 8SOIC
Operating Temperature Range(°C)	-40 to 85	-40 to 85	-40 to 85
ESD HBM(kV)	15	8	8
Approx. Price (US$)	0.85 | 1ku	0.80 | 1ku	0.80 | 1ku

SN65LVDS9637 特性

• Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
• Operate With a Single 3.3-V Supply
• Designed for Signaling Rates of up to100 Mbps
• Differential Input Thresholds ±100 mV Max
• Typical Propagation Delay Time of 2.1 ns
• Power Dissipation 60 mW Typical Per Receiver at Maximum Data Rate
• Bus-Terminal ESD Protection Exceeds 8 kV
• Low-Voltage TTL (LVTTL) Logic Output Levels
• Pin Compatible With AM26LS32, MC3486, and uA9637
• Open-Circuit Fail-Safe
• Cold Sparing for Space and High Reliability Applications Requiring Redundancy

SN65LVDS9637 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN65LVDS9637D	ACTIVE	-40 to 85	1.05 | 1ku	SOIC (D) | 8	75 | TUBE
SN65LVDS9637DG4	ACTIVE	-40 to 85	1.05 | 1ku	SOIC (D) | 8	75 | TUBE
SN65LVDS9637DR	ACTIVE	-40 to 85	0.85 | 1ku	SOIC (D) | 8	2500 | LARGE T&R
SN65LVDS9637DRG4	ACTIVE	-40 to 85	0.85 | 1ku	SOIC (D) | 8	2500 | LARGE T&R

SN65LVDS9637 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN65LVDS9637D	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN65LVDS9637D	SN65LVDS9637D
SN65LVDS9637DG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN65LVDS9637DG4	SN65LVDS9637DG4
SN65LVDS9637DR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN65LVDS9637DR	SN65LVDS9637DR
SN65LVDS9637DRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN65LVDS9637DRG4	SN65LVDS9637DRG4

SN65LVDS9637 应用技术支持与电子电路设计开发资源下载

1. SN65LVDS9637 数据资料 dataSheet 下载.PDF
2. TI 德州仪器LVDS PHYs选型与价格 . xls
3. 所选封装材料的热学和电学性质 (PDF 645 KB)
4. 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
5. 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
6. 接口选择指南 (Rev. D) (PDF 2994 KB)
7. Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
8. Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
9. Isolated RS-485 Reference Design (PDF 80 KB)
10. 无铅组件涂层的保存期评估 (PDF 1305 KB)
11. Analog Signal Chain Guide (8.62 MB)
12. Industrial Interface IC Solutions (101 KB)