SN65LVDS3487 具有 -2 至 4.4V 常见模式范围的四路 LVDS 接收器
The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100
SN65LVDS3487
Input Signal
LVDS
Output Signal
LVTTL
No. of Rx
4
Signaling Rate(Mbps)
400
Supply Voltage(s)(V)
3.3
ICC(Max)(mA)
35
Rx tpd(Typ)(ns)
1.7
Part-to-Part Skew(Max)(ps)
800
Pin/Package
16SOIC
Operating Temperature Range(°C)
-40 to 85
ESD HBM(kV)
8
Approx. Price (US$)
1.20 | 1ku
SN65LVDS3487 特性
Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and 100- Typical Output Voltage Rise and Fall Times of 500 ps (400 Mbps)
Typical Propagation Delay Times of 1.7 ns
Operate From a Single 3.3-V Supply
Power Dissipation 25 mW Typical Per Driver at 200 MHz
Driver at High Impedance When Disabled or With VCC = 0
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Input Levels
Pin Compatible With AM26LS31, MC3487, and uA9638
Cold Sparing for Space and High Reliability Applications Requiring Redundancy
SN65LVDS3487 芯片订购指南
器件
状态
温度
价格
封装 | 引脚
封装数量 | 封装载体
丝印标记
SN65LVDS3487D
ACTIVE
-40 to 85
1.45 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDS3487DG4
ACTIVE
-40 to 85
1.45 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDS3487DR
ACTIVE
-40 to 85
1.20 | 1ku
SOIC (D) | 16 2500 | LARGE T&R
SN65LVDS3487DRG4
ACTIVE
-40 to 85
1.20 | 1ku
SOIC (D) | 16 2500 | LARGE T&R
SN65LVDS3487 质量与无铅数据
器件
环保计划*
铅/焊球涂层
MSL 等级/回流焊峰
环保信息与无铅 (Pb-free)
DPPM / MTBF / FIT 率
SN65LVDS3487D
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3487D
SN65LVDS3487D
SN65LVDS3487DG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3487DG4 SN65LVDS3487DG4
SN65LVDS3487DR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3487DR
SN65LVDS3487DR
SN65LVDS3487DRG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3487DRG4 SN65LVDS3487DRG4
SN65LVDS3487 应用技术支持与电子电路设计开发资源下载
SN65LVDS3487 数据资料 dataSheet 下载 .PDF TI 德州仪器LVDS PHYs选型与价格 . xls 所选封装材料的热学和电学性质 (PDF 645 KB)使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)接口选择指南 (Rev. D) (PDF 2994 KB)Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)Isolated RS-485 Reference Design (PDF 80 KB)无铅组件涂层的保存期评估 (PDF 1305 KB)Analog Signal Chain Guide (8.62 MB)Industrial Interface IC Solutions (101 KB)
The SN55LVDS31, SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 are differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-
load when enabled.