SN65LVDS179-EP 高速差动线路驱动器和接收器

The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100- load, and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.)

The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state, but rather disconnects the input and reduces the quiescent power used by the device. (For these functions with a high-impedance driver output, see the SN65LVDM series of devices.) All devices are characterized for operation from -55°C to 125°C

	SN65LVDS179-EP
Input Signal	LVDS,LVTTL
Output Signal	LVDS,LVTTL
No. of Rx	1
No. of Tx	1
Signaling Rate(Mbps)	400
Supply Voltage(s)(V)	3.3
ICC(Max)(mA)	12
Rx tpd(Typ)(ns)	3.7
Tx tpd(Typ)(ns)	1.7
Pin/Package	8MSOP
Operating Temperature Range(°C)	-55 to 125
ESD HBM(kV)	12

SN65LVDS179-EP 特性

• Controlled Baseline
  • One Assembly/Test Site, One Fabrication Site
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree(1)
• Meet or Exceed the Requirements of ANSI TIA/EIA-644-1995 Standard
• Signaling Rates up to 400 Mbps
• Bus-Terminal ESD Exceeds 12 kV
• Operates From a Single 3.3-V Supply
• Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100- Load
• Propagation Delay Times
  • Driver: 1.7 ns Typ
  • Receiver: 3.7 ns Typ
• Power Dissipation at 200 MHz
  • Driver: 25 mW Typical
  • Receiver: 60 mW Typical
• LVTTL Input Levels Are 5-V Tolerant
• Receiver Maintains High Input Impedance With VCC < 1.5 V
• Receiver Has Open-Circuit Fail Safe

SN65LVDS179-EP 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN65LVDS179MDGKREP	ACTIVE	-55 to 125	3.08 | 100u	MSOP (DGK) | 8	2500 | LARGE T&R
V62/07612-03NE	ACTIVE	-55 to 125	3.08 | 100u	MSOP (DGK) | 8	2500 | LARGE T&R

SN65LVDS179-EP 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN65LVDS179MDGKREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN65LVDS179MDGKREP	SN65LVDS179MDGKREP
V62/07612-03NE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/07612-03NE	V62/07612-03NE

SN65LVDS179-EP 应用技术支持与电子电路设计开发资源下载

1. SN65LVDS179-EP 数据资料 dataSheet 下载.PDF
2. TI 德州仪器LVDS PHYs选型与价格 . xls
3. 所选封装材料的热学和电学性质 (PDF 645 KB)
4. 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
5. 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
6. 接口选择指南 (Rev. D) (PDF 2994 KB)
7. Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
8. Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
9. Isolated RS-485 Reference Design (PDF 80 KB)
10. 无铅组件涂层的保存期评估 (PDF 1305 KB)
11. Analog Signal Chain Guide (8.62 MB)
12. Industrial Interface IC Solutions (101 KB)