SN65LVDS117 双路 8 端口 LVDS 中继器

The SN65LVDS109 and SN65LVDS117 are configured as two identical banks, each bank having one differential line receiver connected to either four ('109) or eight ('117) differential line drivers. The outputs are arranged in pairs having one output from each of the two banks. Individual output enables are provided for each pair of outputs and an additional enable is provided for all outputs.

The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics

	SN65LVDS117
Input Signal	LVDS
Output Signal	LVDS
No. of Rx	2
No. of Tx	16
Signaling Rate(Mbps)	400
Supply Voltage(s)(V)	3.3
ICC(Max)(mA)	122
Tx tpd(Typ)(ns)	2.8
Part-to-Part Skew(Max)(ps)	1500
Pin/Package	64TSSOP
Operating Temperature Range(°C)	-40 to 85
ESD HBM(kV)	12
Approx. Price (US$)	4.50 | 1ku

SN65LVDS117 特性

• Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
• Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
• Outputs Arranged in Pairs From Each Bank
• Enabling Logic Allows Individual Control of Each Driver Output Pair, Plus All Outputs
• Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100

SN65LVDS117 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN65LVDS117DGG	ACTIVE	-40 to 85	5.40 | 1ku	TSSOP (DGG) | 64	25 | TUBE
SN65LVDS117DGGG4	ACTIVE	-40 to 85	5.40 | 1ku	TSSOP (DGG) | 64	25 | TUBE
SN65LVDS117DGGR	ACTIVE	-40 to 85	4.50 | 1ku	TSSOP (DGG) | 64	2000 | LARGE T&R
SN65LVDS117DGGRG4	ACTIVE	-40 to 85	4.50 | 1ku	TSSOP (DGG) | 64	2000 | LARGE T&R

SN65LVDS117 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN65LVDS117DGG	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65LVDS117DGG	SN65LVDS117DGG
SN65LVDS117DGGG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65LVDS117DGGG4	SN65LVDS117DGGG4
SN65LVDS117DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65LVDS117DGGR	SN65LVDS117DGGR
SN65LVDS117DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65LVDS117DGGRG4	SN65LVDS117DGGRG4

SN65LVDS117 应用技术支持与电子电路设计开发资源下载

1. SN65LVDS117 数据资料 dataSheet 下载.PDF
2. TI 德州仪器LVDS PHYs选型与价格 . xls
3. 所选封装材料的热学和电学性质 (PDF 645 KB)
4. 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
5. 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
6. 接口选择指南 (Rev. D) (PDF 2994 KB)
7. Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
8. Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
9. Isolated RS-485 Reference Design (PDF 80 KB)
10. 无铅组件涂层的保存期评估 (PDF 1305 KB)
11. Analog Signal Chain Guide (8.62 MB)
12. Industrial Interface IC Solutions (101 KB)