SN65LVDM180 全双工 LVDM 收发器

The SN65LVDM180, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve high signaling rates. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV across a 50- load simulating two transmission lines in parallel. This allows having data buses with more than one driver or with two line termination resistors. The receivers detect a voltage difference of 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of these devices and signaling techniques is point-to-point half duplex, baseband data transmission over a controlled impedance media of approximately 100 characteristic impedance

	SN65LVDM180	SN65LVDM180	SN65LVDS179	SN65LVDS180
Input Signal	LVDM, LVTTL	LVDM, LVTTL	LVDS, LVTTL	LVDS, LVTTL
Output Signal	LVDM, LVTTL	LVDM, LVTTL	LVDS, LVTTL	LVDS, LVTTL
No. of Rx	1	1	1	1
No. of Tx	1	1	1	1
Signaling Rate(Mbps)	500TX/150RX	500TX/150RX	400TX/150RX	400TX/150RX
Supply Voltage(s)(V)	3.3	3.3	3.3	3.3
ICC(Max)(mA)	15	13	12	12
Rx tpd(Typ)(ns)	3.7	3.7	3.7	3.7
Tx tpd(Typ)(ns)	1.7	1.7	1.7	1.7
Part-to-Part Skew(Max)(ps)	1000	1000
Pin/Package	8MSOP, 8SOIC	14SOIC, 14TSSOP	8MSOP, 8SOIC	14SOIC, 14TSSOP
Operating Temperature Range(°C)	-40 to 85	-40 to 85	-40 to 85	-40 to 85
ESD HBM(kV)	12	12	12	12
Approx. Price (US$)	1.20 | 1ku	1.20 | 1ku	1.35 | 1ku	1.35 | 1ku

SN65LVDM180 特性

• Low-Voltage Differential 50- Line Drivers and Receivers
• Typical Full-Duplex Signaling Rates of 100 Mbps
• Bus-Terminal ESD Exceeds 12 kV
• Operates From a Single 3.3-V Supply
• Low-Voltage Differential Signaling With Typical Output Voltages of 340 mV With a 50- Load
• Valid Output With as Little as 50-mV Input Voltage Difference
• Propagation Delay Times
  • Driver: 1.7 ns Typical
  • Receiver: 3.7 ns Typical
• Power Dissipation at 200 MHz
  • Driver: 50 mW Typical
  • Receiver: 60 mW Typical
• LVTTL Input Levels Are 5-V Tolerant
• Driver Is High Impedance When Disabled or With VCC < 1.5 V
• Receiver Has Open-Circuit Failsafe

SN65LVDM180 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN65LVDM180D	ACTIVE	-40 to 85	1.45 | 1ku	SOIC (D) | 14	50 | TUBE
SN65LVDM180DG4	ACTIVE	-40 to 85	1.45 | 1ku	SOIC (D) | 14	50 | TUBE
SN65LVDM180DR	ACTIVE	-40 to 85	1.20 | 1ku	SOIC (D) | 14	2500 | LARGE T&R
SN65LVDM180DRG4	ACTIVE	-40 to 85	1.20 | 1ku	SOIC (D) | 14	2500 | LARGE T&R

SN65LVDM180 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN65LVDM180D	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN65LVDM180D	SN65LVDM180D
SN65LVDM180DG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN65LVDM180DG4	SN65LVDM180DG4
SN65LVDM180DR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN65LVDM180DR	SN65LVDM180DR
SN65LVDM180DRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN65LVDM180DRG4	SN65LVDM180DRG4

SN65LVDM180 应用技术支持与电子电路设计开发资源下载

1. TI 德州仪器LVDS PHYs选型与价格 . xls
2. 所选封装材料的热学和电学性质 (PDF 645 KB)
3. 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
4. 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
5. 接口选择指南 (Rev. D) (PDF 2994 KB)
6. Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
7. Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
8. Isolated RS-485 Reference Design (PDF 80 KB)
9. 无铅组件涂层的保存期评估 (PDF 1305 KB)
10. Analog Signal Chain Guide (8.62 MB)
11. Industrial Interface IC Solutions (101 KB)