SN54LVC86A 四路 2 输入异或门
The SN54LVC86A quadruple 2-input exclusive-OR gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC86A quadruple 2-input exclusive-OR gate is designed for 1.65-V to 3.6-V VCC operation.
The ’LVC86A devices perform the Boolean function Y = A 
B or Y = A\B + AB\ in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment
| SN54LVC86A | |
| Technology Family | LVC |
SN54LVC86A 特性
- Operate From 1.65 V to 3.6 V
- Specified From -40°C to 85°C, -40°C to 125°C, and -55°C to 125°C
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.6 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN54LVC86A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SNJ54LVC86AFK | ACTIVE | -55 to 125 | 6.83 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54LVC86AJ | ACTIVE | -55 to 125 | 2.20 | 1ku | CDIP (J) | 14 | 1 | TUBE | |
| SNJ54LVC86AW | ACTIVE | -55 to 125 | 6.83 | 1ku | CFP (W) | 14 | 1 | TUBE |
SN54LVC86A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SNJ54LVC86AFK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LVC86AFK | SNJ54LVC86AFK |
| SNJ54LVC86AJ | TBD | A42 | N/A for Pkg Type | SNJ54LVC86AJ | SNJ54LVC86AJ |
| SNJ54LVC86AW | TBD | A42 | N/A for Pkg Type | SNJ54LVC86AW | SNJ54LVC86AW |
SN54LVC86A 应用技术支持与电子电路设计开发资源下载
- SN54LVC86A 数据资料 dataSheet 下载.PDF
- TI 德州仪器门电路产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)