The SN54LVC374A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC374A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state
SN54LVC374A | |
Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
Rating | Military |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SNJ54LVC374AFK | ACTIVE | -55 to 125 | 9.75 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
SNJ54LVC374AJ | ACTIVE | -55 to 125 | 5.95 | 1ku | CDIP (J) | 20 | 1 | TUBE | |
SNJ54LVC374AWD | ACTIVE | -55 to 125 | 10.35 | 1ku | CFP (W) | 20 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SNJ54LVC374AFK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LVC374AFK | SNJ54LVC374AFK |
SNJ54LVC374AJ | TBD | A42 | N/A for Pkg Type | SNJ54LVC374AJ | SNJ54LVC374AJ |
SNJ54LVC374AWD | TBD | Call TI | N/A for Pkg Type | SNJ54LVC374AWD | SNJ54LVC374AWD |