The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components
SN54LVC373A | |
Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
Rating | Military |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SNJ54LVC373AFK | ACTIVE | 5962-9074601M2A | 19.16 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
SNJ54LVC373AJ | ACTIVE | 5962-9074601MRA | 12.02 | 1ku | CDIP (J) | 20 | 1 | TUBE | |
SNJ54LVC373AW | ACTIVE | 5962-9074601MSA | 13.44 | 1ku | CFP (W) | 20 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SNJ54LVC373AFK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LVC373AFK | SNJ54LVC373AFK |
SNJ54LVC373AJ | TBD | A42 | N/A for Pkg Type | SNJ54LVC373AJ | SNJ54LVC373AJ |
SNJ54LVC373AW | TBD | Call TI | N/A for Pkg Type | SNJ54LVC373AW | SNJ54LVC373AW |