SN54LVC32A 四路 2 输入正或门
The SN54LVC32A quadruple 2-input positive-OR gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC32A quadruple 2-input positive-OR gate is designed for 1.65-V to 3.6-V VCC operation.
The ’LVC32A devices perform the Boolean function Y = A + B or Y = (A\ o B\)\ in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment
| SN54LVC32A | |
| Rating | Military |
| Technology Family | LVC |
SN54LVC32A 特性
- Operate From 1.65 V to 3.6 V
- Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C
- Inputs Accept Voltages to 5.5 V
- Max tpd of 3.8 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN54LVC32A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SNJ54LVC32AFK | ACTIVE | -55 to 125 | 12.28 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54LVC32AJ | ACTIVE | -55 to 125 | 4.37 | 1ku | CDIP (J) | 14 | 1 | TUBE | |
| SNJ54LVC32AW | ACTIVE | -55 to 125 | 12.28 | 1ku | CFP (W) | 14 | 1 | TUBE |
SN54LVC32A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SNJ54LVC32AFK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LVC32AFK | SNJ54LVC32AFK |
| SNJ54LVC32AJ | TBD | A42 | N/A for Pkg Type | SNJ54LVC32AJ | SNJ54LVC32AJ |
| SNJ54LVC32AW | TBD | A42 | N/A for Pkg Type | SNJ54LVC32AW | SNJ54LVC32AW |
SN54LVC32A 应用技术支持与电子电路设计开发资源下载
- SN54LVC32A 数据资料 dataSheet 下载.PDF
- TI 德州仪器门电路产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)