SN54LS93 4 位二进制计数器
Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '90A and 'LS90, divide-by-six for the '92A and 'LS92, and the divide-by eight for the '93A and 'LS93.
All of these counters have a gated zero reset and the '90A and 'LS90 also have gated set-to-nine inputs for use in BCD nine's complement applications.
To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the QA output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table
| SN54LS93 | |
| Rating | Military |
| Technology Family | LS |
SN54LS93 特性
- '90A, 'LS90 . . . Decade Counters
- '92A, 'LS92 . . . Divide By-Twelve Counters
- '93A, 'LS93 . . . 4-Bit Binary Counters
SN54LS93 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54LS93J | ACTIVE | -55 to 125 | 1.91 | 1ku | CDIP (J) | 14 | 1 | TUBE | |
| SNJ54LS93FK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54LS93J | ACTIVE | -55 to 125 | 3.46 | 1ku | CDIP (J) | 14 | 1 | TUBE | |
| SNJ54LS93W | ACTIVE | -55 to 125 | 15.12 | 1ku | CFP (W) | 14 | 1 | TUBE |
SN54LS93 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54LS93J | TBD | A42 | N/A for Pkg Type | SN54LS93J | SN54LS93J |
| SNJ54LS93FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS93FK | SNJ54LS93FK |
| SNJ54LS93J | TBD | A42 | N/A for Pkg Type | SNJ54LS93J | SNJ54LS93J |
| SNJ54LS93W | TBD | A42 | N/A for Pkg Type | SNJ54LS93W | SNJ54LS93W |
SN54LS93 应用技术支持与电子电路设计开发资源下载
- SN54LS93 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)