SN54LS76A 具有预设和清零功能的双路 D 类上升沿触发器

The '76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The '76 is a positive-edge-triggered flip-flop. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS76A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table

	SN54LS76A
Voltage Nodes(V)	5
Rating	Military

SN54LS76A 特性

Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages
Dependable Texas Instruments Quality and Reliability

SN54LS76A 芯片订购指南

器件	状态	温度	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体	丝印标记
SN54LS76AJ	ACTIVE	-55 to 125	4.24 \| 1ku	CDIP (J) \| 14	1 \| TUBE

SN54LS76A 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN54LS76AJ	TBD	A42	N/A for Pkg Type	SN54LS76AJ	SN54LS76AJ

SN54LS76A 应用技术支持与电子电路设计开发资源下载

SN54LS76A 数据资料 dataSheet 下载.PDF
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