SN54LS697 具有输出寄存器和多路复用三态输出的同步加/减计数器
These low-power Schottky LSI devices incorporate synchronous up/down counters, four-bit D-type registers, and quadruple two-line to one-line multiplexers with three state outputs in a single 20-pin package. The up/down counters are programmable from the data inputs and feature enable P\ and enable T\ and a ripple-carry output for easy expansion. The register/counter select input R/C\, selects the counter when low and the register when high for the three-state outputs, QA, QB, QC, and QD. These outputs are rated at 12 and 24 milliamperes (54LS/74LS) for good bus driving performance.
Both the counter CCK and register clock RCK are positive-edge triggered. The counter clear CCLR\ is active low and is asynchronous on the 'LS696 and 'LS697, synchronous on the 'LS699
|
SN54LS697 |
| Rating |
Military |
| Technology Family |
LS |
SN54LS697 特性
- 4-Bit Counters/Registers
- Multiplexed Outputs for Counter or Latched Data
- 3-State Outputs Drive Bus Lines Directly
- 'LS696 … Decade Counter, Direct Clear'LS697…Binary Counter, Direct Clear'LS699…Binary Counter, Synchronous Clear
SN54LS697 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN54LS697J |
ACTIVE |
-55 to 125 |
1.91 | 1ku |
CDIP (J) | 20 |
1 | TUBE |
|
| SNJ54LS697FK |
ACTIVE |
-55 to 125 |
17.37 | 1ku |
LCCC (FK) | 20 |
1 | TUBE |
|
| SNJ54LS697J |
ACTIVE |
-55 to 125 |
3.46 | 1ku |
CDIP (J) | 20 |
1 | TUBE |
|
| SNJ54LS697W |
ACTIVE |
-55 to 125 |
15.12 | 1ku |
CFP (W) | 20 |
1 | TUBE |
|
SN54LS697 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN54LS697J |
TBD |
A42 |
N/A for Pkg Type |
SN54LS697J |
SN54LS697J |
| SNJ54LS697FK |
TBD |
POST-PLATE |
N/A for Pkg Type |
SNJ54LS697FK |
SNJ54LS697FK |
| SNJ54LS697J |
TBD |
A42 |
N/A for Pkg Type |
SNJ54LS697J |
SNJ54LS697J |
| SNJ54LS697W |
TBD |
A42 |
N/A for Pkg Type |
SNJ54LS697W |
SNJ54LS697W |
SN54LS697 应用技术支持与电子电路设计开发资源下载
- SN54LS697 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)