SN54LS670-SP 具有三态输出的 4 x 4 寄存器文件
The SN54LS670 and SN74LS670 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The register file is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits simultaneous writing into one location and reading from another word location.
Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that particular bit location
| SN54LS670-SP | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | TTL |
| Output | 3S |
| No. of Bits | 16 |
| Rating | Space |
| Technology Family | LS |
SN54LS670-SP 特性
- Separate Read/Write Addressing Permits Simultaneous Reading and Writing
- Fast Access Times…Typically 20 ns
- Organized as 4 Words of 4 Bits
- Expandable to 512 Words of n-Bits
- For Use as:
- Scratch-Pad Memory
- Buffer Storage between Processors
- Bit Storage in Fast Multiplication Designs
- 3-State Outputs
- SN54LS170 and SN74LS170 Are Similar But Have Open-Collector Outputs
SN54LS670-SP 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 5962-7704201VEA | ACTIVE | -55 to 125 | 142.98 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| 5962-7704201VFA | ACTIVE | -55 to 125 | 142.98 | 1ku | CFP (WD) | 16 | 1 | TUBE |
SN54LS670-SP 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 5962-7704201VEA | TBD | A42 | N/A for Pkg Type | 5962-7704201VEA | 5962-7704201VEA |
| 5962-7704201VFA | TBD | A42 | N/A for Pkg Type | 5962-7704201VFA | 5962-7704201VFA |
SN54LS670-SP 应用技术支持与电子电路设计开发资源下载
- SN54LS670-SP 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)