These Low-Power Schottky eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. The clear function is synchronous, and a low level at the clear input clears the register on the next low-to-high transition of the clock.
SN54LS323 | |
Technology Family | LS |
Rating | Military |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN54LS323J | ACTIVE | -55 to 125 | 16.23 | 1ku | CDIP (J) | 20 | 1 | TUBE | |
SNJ54LS323FK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
SNJ54LS323J | ACTIVE | -55 to 125 | 23.81 | 1ku | CDIP (J) | 20 | 1 | TUBE | |
SNJ54LS323W | ACTIVE | -55 to 125 | 16.23 | 1ku | CFP (W) | 20 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN54LS323J | TBD | A42 | N/A for Pkg Type | SN54LS323J | SN54LS323J |
SNJ54LS323FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS323FK | SNJ54LS323FK |
SNJ54LS323J | TBD | A42 | N/A for Pkg Type | SNJ54LS323J | SNJ54LS323J |
SNJ54LS323W | TBD | Call TI | N/A for Pkg Type | SNJ54LS323W | SNJ54LS323W |