SN54LS280 9 位奇/偶校验发生器/检测器

These universal, monolithic, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading as shown under typical application data.

Series 54LS/74LS and Series 54S/74S parity generators/checkers offer the designer a trade-off between reduced power consumption and high performance. These devices can be used to upgrade the performance of most systems utilizing the '180 parity generator/checker. Although the 'LS280 and 'S280 are implemented without expander inputs, the corresponding function is provided by the availability of an input at pin 4 and the absence of any internal connection at pin 3

	SN54LS280
Rating	Military
Technology Family	LS

SN54LS280 特性

• Generates Either Odd or Even Parity for Nine Data Lines
• Cascadable for n-Bits
• Can Be Used to Upgrade Existing Systems using MSI Parity Circuits
• Typical Data-to-Output Delay of Only 14 ns for 'S280 and 33 ns for 'LS280
• Typical Power Dissipation:
  • 'LS280 … 80 mW
  • 'S280 … 335 mW

SN54LS280 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN54LS280J	ACTIVE	-55 to 125	4.38 | 1ku	CDIP (J) | 14	1 | TUBE
SNJ54LS280FK	ACTIVE	-55 to 125	12.33 | 1ku	LCCC (FK) | 20	1 | TUBE
SNJ54LS280J	ACTIVE	-55 to 125	5.15 | 1ku	CDIP (J) | 14	1 | TUBE
SNJ54LS280W	ACTIVE	-55 to 125	14.61 | 1ku	CFP (W) | 14	1 | TUBE

SN54LS280 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN54LS280J	TBD	A42	N/A for Pkg Type	SN54LS280J	SN54LS280J
SNJ54LS280FK	TBD	POST-PLATE	N/A for Pkg Type	SNJ54LS280FK	SNJ54LS280FK
SNJ54LS280J	TBD	A42	N/A for Pkg Type	SNJ54LS280J	SNJ54LS280J
SNJ54LS280W	TBD	A42	N/A for Pkg Type	SNJ54LS280W	SNJ54LS280W

SN54LS280 应用技术支持与电子电路设计开发资源下载

1. SN54LS280 数据资料 dataSheet 下载.PDF
2. TI 德州仪器MSI 功能产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)