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SN54LS279A 四路 /S-/R 锁存器

The ’279 offers 4 basic S\-R\ flip-flop latches in one 16-pin, 300-mil package. Under conventional operation, the S\-R\ inputs are normally held high. When the S\ input is pulsed low, the Q output will be set high. When R\ is pulsed low, the Q output will be reset low. Normally, the S\-R\ inputs should not be taken low simultaneously. The Q output will be unpredictable in this condition.

SN54LS279A
Voltage Nodes(V) 5
Vcc range(V) 4.5 to 5.5
Input Level TTL
Output Level TTL
Output Drive(mA)
Output 2S
No. of Bits 4
tpd max(ns)
Rating Military
Technology Family LS
SN54LS279A 特性
SN54LS279A 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN54LS279AJ ACTIVE -55 to 125 6.67 | 1ku CDIP (J) | 16 1 | TUBE  
SNJ54LS279AFK OBSOLETE -55 to 125 LCCC (FK) | 20  
SNJ54LS279AJ ACTIVE -55 to 125 7.88 | 1ku CDIP (J) | 16 1 | TUBE  
SN54LS279A 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN54LS279AJ TBD A42 N/A for Pkg Type SN54LS279AJ SN54LS279AJ
SNJ54LS279AFK TBD POST-PLATE N/A for Pkg Type SNJ54LS279AFK SNJ54LS279AFK
SNJ54LS279AJ TBD A42 N/A for Pkg Type SNJ54LS279AJ SNJ54LS279AJ
SN54LS279A 应用技术支持与电子电路设计开发资源下载
  1. SN54LS279A 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)