SN54LS194A 4 位双向通用移位寄存器
These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:
- Inhibit clock (do nothing)
- Shift right (in the direction QA toward QD)
- Shift left (in the direction QD toward QA)
- Parallel (broadside) load
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input
| SN54LS194A | |
| Technology Family | LS |
| Rating | Military |
SN54LS194A 特性
- Parallel Inputs and Outputs
- Four Operating Modes:
- Synchronous Parallel Load
- Right Shift
- Left Shift
- Do Nothing
- Positive Edge-Triggered Clocking
- Direct Overriding Clear
SN54LS194A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54LS194AJ | ACTIVE | -55 to 125 | 16.23 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS194AFK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54LS194AJ | ACTIVE | -55 to 125 | 23.81 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS194AW | ACTIVE | -55 to 125 | 16.23 | 1ku | CFP (W) | 16 | 1 | TUBE |
SN54LS194A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54LS194AJ | TBD | A42 | N/A for Pkg Type | SN54LS194AJ | SN54LS194AJ |
| SNJ54LS194AFK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS194AFK | SNJ54LS194AFK |
| SNJ54LS194AJ | TBD | A42 | N/A for Pkg Type | SNJ54LS194AJ | SNJ54LS194AJ |
| SNJ54LS194AW | TBD | Call TI | N/A for Pkg Type | SNJ54LS194AW | SNJ54LS194AW |
SN54LS194A 应用技术支持与电子电路设计开发资源下载
- SN54LS194A 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)